From 2ae22ac6cb6e81b7f1e96f9caa1655a489348f48 Mon Sep 17 00:00:00 2001 From: Daniel Torres Date: Wed, 29 Jun 2022 12:23:40 -0700 Subject: [PATCH] added changes to testbench, tests and riscof for additional riscof compatability --- pipelined/testbench/testbench.sv | 6 +- pipelined/testbench/tests.vh | 119 ++++++++++----------- tests/riscof/Makefile | 32 ++++-- tests/riscof/sail_cSim/riscof_sail_cSim.py | 2 +- tests/riscof/spike/spike_rv32imc_isa.yaml | 9 +- 5 files changed, 94 insertions(+), 74 deletions(-) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 4a6874c44..1f4f70a08 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -68,6 +68,7 @@ logic [3:0] dummy; integer ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 }; logic DCacheFlushDone, DCacheFlushStart; + logic riscofTest; flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW); flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW); @@ -174,6 +175,8 @@ logic [3:0] dummy; totalerrors = 0; testadr = 0; testadrNoBase = 0; + // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests and tests[0] == "2" refers to WallyRiscvArchTests + riscofTest = tests[0] == "1"; // | tests[0] == "2"; // fill memory with defined values to reduce Xs in simulation // Quick note the memory will need to be initialized. The C library does not // guarantee the initialized reads. For example a strcmp can read 6 byte @@ -250,8 +253,7 @@ logic [3:0] dummy; for(i=0; i config$(XLEN).ini + +build_arch: riscof run --work-dir=$(work_dir) --config=config$(XLEN).ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser - rm -rf work/rv$(XLEN)i_m - mv -f $(work_dir)/rv$(XLEN)i_m work/ + rm -rf $(arch_workdir)/rv$(XLEN)i_m + mv -f $(work_dir)/rv$(XLEN)i_m $(arch_workdir)/ + +build_wally: + riscof --verbose debug run --work-dir=$(work_dir) --config=config$(XLEN).ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run + rm -rf $(wally_workdir)/rv$(XLEN)i_m + mv -f $(work_dir)/rv$(XLEN)i_m $(wally_workdir)/ + +memfile: + find $(work) -type f -name "*.elf" | grep "rv64i_m" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 64 --input "$$f" --output "$$f.memfile"; done + find $(work) -type f -name "*.elf" | grep "rv32i_m" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 32 --input "$$f" --output "$$f.memfile"; done + find $(work) -type f -name "*.elf.objdump" | while read f; do extractFunctionRadix.sh $$f; done clean: rm -f config64.ini rm -f config32.ini rm -rf $(work_dir) - rm -rf work \ No newline at end of file + rm -rf $(wally_workdir) + rm -rf $(arch_workdir) \ No newline at end of file diff --git a/tests/riscof/sail_cSim/riscof_sail_cSim.py b/tests/riscof/sail_cSim/riscof_sail_cSim.py index 7a7d16afb..b86f62b55 100644 --- a/tests/riscof/sail_cSim/riscof_sail_cSim.py +++ b/tests/riscof/sail_cSim/riscof_sail_cSim.py @@ -101,7 +101,7 @@ class sail_cSim(pluginTemplate): execute += self.objdump_cmd.format(elf, self.xlen, 'Ref.elf.objdump') sig_file = os.path.join(test_dir, self.name[:-1] + ".signature") - execute += self.sail_exe[self.xlen] + ' --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name) + execute += self.sail_exe[self.xlen] + ' -z268435455 --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name) cov_str = ' ' for label in testentry['coverage_labels']: diff --git a/tests/riscof/spike/spike_rv32imc_isa.yaml b/tests/riscof/spike/spike_rv32imc_isa.yaml index 644e97316..5a76fd978 100644 --- a/tests/riscof/spike/spike_rv32imc_isa.yaml +++ b/tests/riscof/spike/spike_rv32imc_isa.yaml @@ -1,11 +1,11 @@ hart_ids: [0] hart0: - ISA: RV32IMFCZicsr_Zifencei + ISA: RV32IMAFCZicsr_Zifencei physical_addr_sz: 32 User_Spec_Version: '2.3' supported_xlen: [32] misa: - reset-val: 0x40001124 + reset-val: 0x40001125 rv32: accessible: true mxl: @@ -23,7 +23,6 @@ hart0: warl: dependency_fields: [] legal: - - extensions[25:0] bitmask [0x0001124, 0x0000000] + - extensions[25:0] bitmask [0x0001125, 0x0000000] wr_illegal: - - Unchanged - + - Unchanged \ No newline at end of file