diff --git a/wally-pipelined/src/fpu/divconv_pipe.sv b/wally-pipelined/src/fpu/divconv_pipe.sv index 3388acc3f..240000c28 100755 --- a/wally-pipelined/src/fpu/divconv_pipe.sv +++ b/wally-pipelined/src/fpu/divconv_pipe.sv @@ -66,8 +66,6 @@ module divconv_pipe (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, r logic [59:0] d2, n2; logic [11:0] d3; - logic cout1, cout2, cout3, cout4, cout5, cout6, cout7; - // Check if exponent is odd for sqrt // If exp_odd=1 and sqrt, then M/2 and use ia_addr=0 as IA assign d2 = (exp_odd&op_type) ? {vss, d, 6'h0} : {d, 7'h0}; diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv index 1e8c7cbf1..2ebd65d82 100644 --- a/wally-pipelined/src/ieu/datapath.sv +++ b/wally-pipelined/src/ieu/datapath.sv @@ -38,7 +38,6 @@ module datapath ( input logic TargetSrcE, input logic JumpE, input logic IllegalFPUInstrE, - input logic [1:0] MemRWE, input logic [`XLEN-1:0] FWriteDataE, input logic [`XLEN-1:0] PCE, input logic [`XLEN-1:0] PCLinkE, @@ -84,7 +83,6 @@ module datapath ( logic [`XLEN-1:0] ResultM; // Writeback stage signals logic [`XLEN-1:0] SCResultW; - logic [`XLEN-1:0] ALUResultW; logic [`XLEN-1:0] WriteDataW; logic [`XLEN-1:0] ResultW; @@ -143,12 +141,5 @@ module datapath ( .d(ReadDataM), .q(ReadDataW)); - mux5 #(`XLEN) resultmuxW(ResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, WriteDataW); -/* -----\/----- EXCLUDED -----\/----- - // This mux4:1 no longer needs to include PCLinkW. This is set correctly in the execution stage. - // *** need to look at how the decoder is coded to fix. - mux4 #(`XLEN) resultmux(ALUResultW, ReadDataW, PCLinkW, CSRReadValW, ResultSrcW, WriteDataW); ->>>>>>> bp - -----/\----- EXCLUDED -----/\----- */ - + mux5 #(`XLEN) resultmuxW(ResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, WriteDataW); endmodule diff --git a/wally-pipelined/src/ieu/forward.sv b/wally-pipelined/src/ieu/forward.sv index 3e25ca7cc..cab6c3ed2 100644 --- a/wally-pipelined/src/ieu/forward.sv +++ b/wally-pipelined/src/ieu/forward.sv @@ -30,10 +30,8 @@ module forward( input logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW, input logic MemReadE, MulDivE, CSRReadE, input logic RegWriteM, RegWriteW, - input logic DivBusyE, input logic FWriteIntE, FWriteIntM, FWriteIntW, input logic SCE, - input logic StallD, // Forwarding controls output logic [1:0] ForwardAE, ForwardBE, output logic FPUStallD, LoadStallD, MulDivStallD, CSRRdStallD diff --git a/wally-pipelined/src/muldiv/intdivrestoring.sv b/wally-pipelined/src/muldiv/intdivrestoring.sv index dd92c9692..806015f1f 100644 --- a/wally-pipelined/src/muldiv/intdivrestoring.sv +++ b/wally-pipelined/src/muldiv/intdivrestoring.sv @@ -30,7 +30,7 @@ module intdivrestoring ( input logic clk, input logic reset, - input logic StallM, FlushM, + input logic StallM, input logic DivSignedE, W64E, input logic DivE, input logic [`XLEN-1:0] SrcAE, SrcBE, @@ -47,7 +47,7 @@ module intdivrestoring ( localparam STEPBITS = $clog2(`XLEN/`DIV_BITSPERCYCLE); logic [STEPBITS:0] step; logic Div0E, Div0M; - logic DivStartE, SignXE, SignXM, SignDE, NegQE, NegWM, NegQM; + logic DivStartE, SignXE, SignDE, NegQE, NegWM, NegQM; logic [`XLEN-1:0] WNextE, XQNextE; ////////////////////////////// diff --git a/wally-pipelined/src/muldiv/mul.sv b/wally-pipelined/src/muldiv/mul.sv index 5ab8b73ad..dee645d39 100644 --- a/wally-pipelined/src/muldiv/mul.sv +++ b/wally-pipelined/src/muldiv/mul.sv @@ -50,10 +50,9 @@ module mul ( logic [`XLEN*2-1:0] PP0E, PP1E, PP2E, PP3E, PP4E; logic [`XLEN*2-1:0] PP0M, PP1M, PP2M, PP3M, PP4M; - logic [`XLEN*2-1:0] Pprime; logic [`XLEN-2:0] PA, PB; logic PP; - logic MULH, MULHSU, MULHU; + logic MULH, MULHSU; logic [`XLEN-1:0] Aprime, Bprime; ////////////////////////////// @@ -70,7 +69,6 @@ module mul ( // flavor of multiplication assign MULH = (Funct3E == 3'b001); assign MULHSU = (Funct3E == 3'b010); - // assign MULHU = (Funct3E == 2'b11); // signal unused // Handle signs assign PP2E = {2'b00, (MULH | MULHSU) ? ~PA : PA, {(`XLEN-1){1'b0}}}; diff --git a/wally-pipelined/src/muldiv/muldiv.sv b/wally-pipelined/src/muldiv/muldiv.sv index 5ef88bb18..4bad2d301 100644 --- a/wally-pipelined/src/muldiv/muldiv.sv +++ b/wally-pipelined/src/muldiv/muldiv.sv @@ -59,7 +59,7 @@ module muldiv ( // Start a divide when a new division instruction is received and the divider isn't already busy or finishing assign DivE = MulDivE & Funct3E[2]; assign DivSignedE = ~Funct3E[0]; - intdivrestoring div(.clk, .reset, .StallM, .FlushM, + intdivrestoring div(.clk, .reset, .StallM, .DivSignedE, .W64E, .DivE, .SrcAE, .SrcBE, .DivBusyE, .QuotM, .RemM); // Result multiplexer diff --git a/wally-pipelined/src/uncore/dtim.sv b/wally-pipelined/src/uncore/dtim.sv index c195c5516..a331055cf 100644 --- a/wally-pipelined/src/uncore/dtim.sv +++ b/wally-pipelined/src/uncore/dtim.sv @@ -44,18 +44,16 @@ module dtim #(parameter BASE=0, RANGE = 65535) ( logic [31:0] HWADDR, A; logic [`XLEN-1:0] HREADTim0; -// logic [`XLEN-1:0] write; logic prevHREADYTim, risingHREADYTim; logic initTrans; logic [15:0] entry; - logic memread, memwrite; + logic memwrite; logic [3:0] busycount; assign initTrans = HREADY & HSELTim & (HTRANS != 2'b00); // *** this seems like a weird way to use reset - flopenr #(1) memreadreg(HCLK, 1'b0, initTrans | ~HRESETn, HSELTim & ~HWRITE, memread); flopenr #(1) memwritereg(HCLK, 1'b0, initTrans | ~HRESETn, HSELTim & HWRITE, memwrite); flopenr #(32) haddrreg(HCLK, 1'b0, initTrans | ~HRESETn, HADDR, A); diff --git a/wally-pipelined/src/uncore/gpio.sv b/wally-pipelined/src/uncore/gpio.sv index 0100c9c56..21810de9d 100644 --- a/wally-pipelined/src/uncore/gpio.sv +++ b/wally-pipelined/src/uncore/gpio.sv @@ -45,14 +45,13 @@ module gpio ( logic [31:0] input_val, input_en, output_en, output_val; logic [31:0] rise_ie, rise_ip, fall_ie, fall_ip, high_ie, high_ip, low_ie, low_ip; - logic initTrans, memread, memwrite; - logic [7:0] entry, entryd, HADDRd; + logic initTrans, memwrite; + logic [7:0] entry, entryd; logic [31:0] Din, Dout; // AHB I/O assign entry = {HADDR[7:2],2'b0}; assign initTrans = HREADY & HSELGPIO & (HTRANS != 2'b00); - assign memread = initTrans & ~HWRITE; // entryd and memwrite are delayed by a cycle because AHB controller waits a cycle before outputting write data flopr #(1) memwriteflop(HCLK, ~HRESETn, initTrans & HWRITE, memwrite); flopr #(8) entrydflop(HCLK, ~HRESETn, entry, entryd);