diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv
index 6c52432d9..9d945ef8c 100644
--- a/src/ieu/alu.sv
+++ b/src/ieu/alu.sv
@@ -39,13 +39,13 @@ module alu #(parameter WIDTH=32) (
 
   // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction.
   // FullResult = ALU result before adjusting for a RV64 w-suffix instruction.
-  logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult;  // Intermediate results
-  logic             Carry, Neg;                              // Flags: carry out, negative
-  logic             LT, LTU;                                 // Less than, Less than unsigned
-  logic             W64;                                     // RV64 W-type instruction
-  logic             SubArith;                                // Performing subtraction or arithmetic right shift
-  logic             ALUOp;                                   // 0 for address generation addition or 1 for regular ALU ops
-  logic             Asign, Bsign;                            // Sign bits of A, B
+  logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult;  // Intermediate results
+  logic             Carry, Neg;                                        // Flags: carry out, negative
+  logic             LT, LTU;                                           // Less than, Less than unsigned
+  logic             W64;                                               // RV64 W-type instruction
+  logic             SubArith;                                          // Performing subtraction or arithmetic right shift
+  logic             ALUOp;                                             // 0 for address generation addition or 1 for regular ALU ops
+  logic             Asign, Bsign;                                      // Sign bits of A, B
   logic             rotate;
 
   // Extract control signals from ALUControl.
@@ -86,6 +86,10 @@ module alu #(parameter WIDTH=32) (
     endcase
 
   // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits
-  if (WIDTH == 64)  assign Result = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
-  else              assign Result = FullResult;
+  if (WIDTH == 64)  assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
+  else              assign ALUResult = FullResult;
+
+  if (`ZBC_SUPPORTED) begin
+    
+  end else assign Result = ALUResult;
 endmodule
\ No newline at end of file