diff --git a/sim/imperas.ic b/sim/imperas.ic
index b7f63bcd2..e716d78b6 100644
--- a/sim/imperas.ic
+++ b/sim/imperas.ic
@@ -26,7 +26,7 @@
 --override cpu/Zicboz=T
 --override cmomp_bytes=64  # Zic64b
 --override cmoz_bytes=64   # Zic64b
---override lr_sc_grain=64  # Za64rs
+--override lr_sc_grain=8   # Za64rs requires <=64; we use native word size
 
 # 64 KiB continuous huge pages supported
 --override cpu/Svpbmt=T
diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv
index cfc0a8c16..b67340989 100644
--- a/src/cache/cachefsm.sv
+++ b/src/cache/cachefsm.sv
@@ -79,6 +79,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
   logic              CMOWriteback;
   logic              CMOZeroNoEviction;
   logic              StallConditions;
+  logic              StoreHazard;
 
   typedef enum logic [3:0]{STATE_READY, // hit states
                            // miss states
diff --git a/src/lsu/lrsc.sv b/src/lsu/lrsc.sv
index cc6c94ba8..66a9956dc 100644
--- a/src/lsu/lrsc.sv
+++ b/src/lsu/lrsc.sv
@@ -40,16 +40,20 @@ module lrsc import cvw::*;  #(parameter cvw_t P) (
   output logic                 SquashSCW   // Squash the store conditional by not allowing rf write
 );
 
+  // reservation set size is XLEN for Wally
+  localparam RESERVATION_SET_SIZE_IN_BYTES = P.XLEN/8;
+  localparam RESERVATION_SET_ADDRESS_BITS = $clog2(RESERVATION_SET_SIZE_IN_BYTES); // 2 for rv32, 3 for rv64
+
   // possible bug: *** double check if PreLSURWM needs to be flushed by ignorerequest.
   // Handle atomic load reserved / store conditional
-  logic [P.PA_BITS-1:2]        ReservationPAdrW;
+  logic [P.PA_BITS-1:RESERVATION_SET_ADDRESS_BITS]        ReservationPAdrW;
   logic                        ReservationValidM, ReservationValidW; 
   logic                        lrM, scM, WriteAdrMatchM;
   logic                        SquashSCM;
 
   assign lrM = MemReadM & LSUAtomicM[0];
   assign scM = PreLSURWM[0] & LSUAtomicM[0]; 
-  assign WriteAdrMatchM = PreLSURWM[0] & (PAdrM[P.PA_BITS-1:2] == ReservationPAdrW) & ReservationValidW;
+  assign WriteAdrMatchM = PreLSURWM[0] & (PAdrM[P.PA_BITS-1:RESERVATION_SET_ADDRESS_BITS] == ReservationPAdrW) & ReservationValidW;
   assign SquashSCM = scM & ~WriteAdrMatchM;
   assign LSURWM = SquashSCM ? 2'b00 : PreLSURWM;
   always_comb begin // ReservationValidM (next value of valid reservation)
@@ -59,7 +63,7 @@ module lrsc import cvw::*;  #(parameter cvw_t P) (
     else ReservationValidM = ReservationValidW; // otherwise don't change valid
   end
   
-  flopenr #(P.PA_BITS-2) resadrreg(clk, reset, lrM & ~StallW, PAdrM[P.PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
+  flopenr #(P.PA_BITS-RESERVATION_SET_ADDRESS_BITS) resadrreg(clk, reset, lrM & ~StallW, PAdrM[P.PA_BITS-1:RESERVATION_SET_ADDRESS_BITS], ReservationPAdrW); // could drop clear on this one but not valid
   flopenr #(1) resvldreg(clk, reset, ~StallW, ReservationValidM, ReservationValidW);
   flopenr #(1) squashreg(clk, reset, ~StallW, SquashSCM, SquashSCW);
 endmodule
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-lrsc-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-lrsc-01.S
index 3cf332f6b..fd8b6ceaa 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-lrsc-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-lrsc-01.S
@@ -48,7 +48,7 @@ RVMODEL_BOOT
 
  # Testcase 1:  Do an unsuccessful load-reserved / store conditional word operation
 	addi x6, x6, 24
-    addi x30, x31, 4
+    addi x30, x31, 8    # 8 bytes later (reservation set size is 8 bytes)
     li x11, 43
     lr.w x10, (x30)
     sc.w x12, x11, (x31)  # should fail because not reserved
@@ -59,7 +59,7 @@ RVMODEL_BOOT
 
     # Testcase 2:  Do a successful load-reserved / store conditional doubleword operation
  	addi x6, x6, 24
-    addi x31, x30, 4
+    addi x31, x30, 8
     li x11, 44
     lr.d x10, (x31)
     sc.d x12, x11, (x31)