From f83e6cf7719e9f073bb75ae08d1289007ec0130e Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 8 Jul 2024 14:48:52 -0500 Subject: [PATCH 1/3] Fixed issue #874. --- testbench/testbench.sv | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index e65fed554..5458681f2 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -462,7 +462,7 @@ module testbench; integer StartIndex; integer EndIndex; integer BaseIndex; - integer memFile; + integer memFile, uncoreMemFile; integer readResult; if (P.SDC_SUPPORTED) begin always @(posedge clk) begin @@ -505,8 +505,16 @@ module testbench; end readResult = $fread(dut.uncoregen.uncore.ram.ram.memory.ram.RAM, memFile); $fclose(memFile); - end else - $readmemh(memfilename, dut.uncoregen.uncore.ram.ram.memory.ram.RAM); + end else begin + uncoreMemFile = $fopen(memfilename, "r"); // Is there a better way to test if a file exists? + if (uncoreMemFile == 0) begin + $display("Error: Could not open file %s", memfilename); + $finish; + end else begin + $fclose(uncoreMemFile); + $readmemh(memfilename, dut.uncoregen.uncore.ram.ram.memory.ram.RAM); + end + end if (TEST == "embench") $display("Read memfile %s", memfilename); end if (CopyRAM) begin From 1a2607c3d93539b12884d07d53617ba808ed06cd Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Thu, 11 Jul 2024 10:53:18 -0500 Subject: [PATCH 2/3] Commented out riscv,isa-extensions from Arty device tree until Linux kernel is updated. --- linux/devicetree/wally-artya7.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux/devicetree/wally-artya7.dts b/linux/devicetree/wally-artya7.dts index 1ad559bbc..490858d96 100644 --- a/linux/devicetree/wally-artya7.dts +++ b/linux/devicetree/wally-artya7.dts @@ -31,7 +31,7 @@ status = "okay"; compatible = "riscv"; riscv,isa = "rv64imafdcsu"; - riscv,isa-extensions = "imafdc", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zicbom", "zicbop", "zicbopz", "zicntr", "zicsr", "zifencei", "zihpm"; + // riscv,isa-extensions = "imafdc", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zicbom", "zicbop", "zicbopz", "zicntr", "zicsr", "zifencei", "zihpm"; mmu-type = "riscv,sv48"; interrupt-controller { From 7f72fb8583627fee4d7b9d120a086adbc10c91c4 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Fri, 12 Jul 2024 09:28:54 -0500 Subject: [PATCH 3/3] Updated riscv,isa-extensions property with the correct syntax. Added riscv,cbom-block-size. --- linux/devicetree/wally-artya7.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/linux/devicetree/wally-artya7.dts b/linux/devicetree/wally-artya7.dts index 490858d96..87933bcc0 100644 --- a/linux/devicetree/wally-artya7.dts +++ b/linux/devicetree/wally-artya7.dts @@ -31,7 +31,9 @@ status = "okay"; compatible = "riscv"; riscv,isa = "rv64imafdcsu"; - // riscv,isa-extensions = "imafdc", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zicbom", "zicbop", "zicbopz", "zicntr", "zicsr", "zifencei", "zihpm"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zicbom", "zicbop", "zicbopz", "zicntr", "zicsr", "zifencei", "zihpm"; + riscv,cbom-block-size = <64>; mmu-type = "riscv,sv48"; interrupt-controller {