Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-02 17:55:19 +00:00
Code Issues Packages Projects Releases Wiki Activity

update hardcoded paths removing HMC/OSU servers: Issue #647

Browse Source
This commit is contained in:
James Stine 2024-09-17 08:49:43 -05:00
parent 9312cfb507
commit 29379d0080
2 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
site-setup.sh
View File

@ -13,13 +13,23 @@ export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change thi
export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server
export IMPERASD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Imperas license server export IMPERASD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Imperas license server
export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim # Change this for your path to Questa, excluding bin export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim # Change this for your path to Questa, excluding bin
export DC_HOME=/cad/synopsys/SYN # Change this for your path to Synopsys Design Compiler, excluding bin export DC_HOME=/cad/synopsys/SYN # Change this for your path to Synopsys DC, excluding bin
export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4 # Change this for your path to Synopsys VCS, excluding bin export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4 # Change this for your path to Synopsys VCS, excluding bin
# Tools # Tools
# Questa and Synopsys # Questa and Synopsys
export PATH=$QUESTA_HOME/bin:$DC_HOME/bin:$VCS_HOME/bin:$PATH export PATH=$QUESTA_HOME/bin:$DC_HOME/bin:$VCS_HOME/bin:$PATH
# Environmental variables for SoC
export pdk=/proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/
#export osupdk=/import/yukari1/pdk/TSMC/28/CMOS/HPC+/stclib/9-track/tcbn28hpcplusbwp30p140-set/tcbn28hpcplusbwp30p140_190a_FE/
export TLU=/home/jstine/TLU+
#export OSUTLU=/import/yukari1/pdk/TSMC/TLU+
export MW=/home/jstine/MW
#export OSUMW=/import/yukari1/pdk/TSMC/MW
export memory=/home/jstine/WallyMem/rv64gc/
#export osumemory=/import/yukari1/pdk/TSMC/WallyMem/rv64gc/
# GCC # GCC
if [ -z "$LD_LIBRARY_PATH" ]; then if [ -z "$LD_LIBRARY_PATH" ]; then
export LD_LIBRARY_PATH=$RISCV/riscv64-unknown-elf/lib export LD_LIBRARY_PATH=$RISCV/riscv64-unknown-elf/lib

14
synthDC/.synopsys_dc.setup
View File

@ -18,23 +18,15 @@ if {$tech == "sky130"} {
set s9lib $timing_lib/sky90/sky90_sc/V1.7.4/lib set s9lib $timing_lib/sky90/sky90_sc/V1.7.4/lib
lappend search_path $s9lib lappend search_path $s9lib
} elseif {$tech == "tsmc28"} { } elseif {$tech == "tsmc28"} {
set pdk /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/
set osupdk /import/yukari1/pdk/TSMC/28/CMOS/HPC+/stclib/9-track/tcbn28hpcplusbwp30p140-set/tcbn28hpcplusbwp30p140_190a_FE/
set s10lib $pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a set s10lib $pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
lappend search_path $s10lib lappend search_path $s10lib
} elseif {$tech == "tsmc28psyn"} { } elseif {$tech == "tsmc28psyn"} {
set TLU /home/jstine/TLU+
set OSUTLU /import/yukari1/pdk/TSMC/TLU+
set pdk /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/
set osupdk /import/yukari1/pdk/TSMC/28/CMOS/HPC+/stclib/9-track/tcbn28hpcplusbwp30p140-set/tcbn28hpcplusbwp30p140_190a_FE/
set s10lib $pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a set s10lib $pdk/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a
lappend search_path $s10lib lappend search_path $s10lib
set TLUPLUS true set TLUPLUS true
set mw_logic1_net VDD set mw_logic1_net VDD
set mw_logic0_net VSS set mw_logic0_net VSS
set CAPTABLE $TLU/1p8m/ set CAPTABLE $TLU/1p8m/
set MW /home/jstine/MW
set OSUMW /import/yukari1/pdk/TSMC/MW
set MW_REFERENCE_LIBRARY $MW set MW_REFERENCE_LIBRARY $MW
set MW_TECH_FILE tcbn28hpcplusbwp30p140 set MW_TECH_FILE tcbn28hpcplusbwp30p140
set MIN_TLU_FILE $CAPTABLE/crn28hpc+_1p08m+ut-alrdl_5x1z1u_rcbest.tluplus set MIN_TLU_FILE $CAPTABLE/crn28hpc+_1p08m+ut-alrdl_5x1z1u_rcbest.tluplus
@ -70,8 +62,6 @@ lappend search_path ./scripts
lappend search_path ./hdl lappend search_path ./hdl
lappend search_path ./mapped lappend search_path ./mapped
if {($tech == "tsmc28psyn")} { if {($tech == "tsmc28psyn")} {
set memory /home/jstine/WallyMem/rv64gc/
set osumemory /import/yukari1/pdk/TSMC/WallyMem/rv64gc/
lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db
lappend target_library $memory/ts1n28hpcpsvtb64x44m4sw_180a/NLDM/ts1n28hpcpsvtb64x44m4sw_tt0p9v25c.db lappend target_library $memory/ts1n28hpcpsvtb64x44m4sw_180a/NLDM/ts1n28hpcpsvtb64x44m4sw_tt0p9v25c.db
lappend target_library $memory/tsdn28hpcpa1024x68m4mw_130a/NLDM/tsdn28hpcpa1024x68m4mw_tt0p9v25c.db lappend target_library $memory/tsdn28hpcpa1024x68m4mw_130a/NLDM/tsdn28hpcpa1024x68m4mw_tt0p9v25c.db
@ -86,8 +76,8 @@ if {($tech == "tsmc28psyn")} {
set link_library "$target_library $synthetic_library" set link_library "$target_library $synthetic_library"
# Set up User Information # Set up User Information
set company "Oklahoma State University" set company "Detect-o-rama"
set user "James E. Stine" set user "Ben Bitbiddle"
# Alias # Alias
alias ra report_area alias ra report_area