mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Major cleanup of bp.
This commit is contained in:
parent
fa49de8391
commit
2920179435
@ -34,9 +34,9 @@ module RASPredictor #(parameter int StackSize = 16 )(
|
|||||||
input logic reset,
|
input logic reset,
|
||||||
input logic StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
|
input logic StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
|
||||||
input logic WrongBPRetD, // Prediction class is wrong
|
input logic WrongBPRetD, // Prediction class is wrong
|
||||||
input logic [3:0] InstrClassD,
|
input logic RetD,
|
||||||
input logic [3:0] InstrClassE, // Instr class
|
input logic RetE, JalE, // Instr class
|
||||||
input logic [3:0] PredInstrClassF,
|
input logic BPRetF,
|
||||||
input logic [`XLEN-1:0] PCLinkE, // PC of instruction after a jal
|
input logic [`XLEN-1:0] PCLinkE, // PC of instruction after a jal
|
||||||
output logic [`XLEN-1:0] RASPCF // Top of the stack
|
output logic [`XLEN-1:0] RASPCF // Top of the stack
|
||||||
);
|
);
|
||||||
@ -58,17 +58,17 @@ module RASPredictor #(parameter int StackSize = 16 )(
|
|||||||
logic WrongPredRetD;
|
logic WrongPredRetD;
|
||||||
|
|
||||||
|
|
||||||
assign PopF = PredInstrClassF[2] & ~StallD & ~FlushD;
|
assign PopF = BPRetF & ~StallD & ~FlushD;
|
||||||
assign PushE = InstrClassE[3] & ~StallM & ~FlushM;
|
assign PushE = JalE & ~StallM & ~FlushM;
|
||||||
|
|
||||||
assign WrongPredRetD = (WrongBPRetD) & ~StallE & ~FlushE;
|
assign WrongPredRetD = (WrongBPRetD) & ~StallE & ~FlushE;
|
||||||
assign FlushedRetDE = (~StallE & FlushE & InstrClassD[2]) | (~StallM & FlushM & InstrClassE[2]); // flushed ret
|
assign FlushedRetDE = (~StallE & FlushE & RetD) | (~StallM & FlushM & RetE); // flushed ret
|
||||||
|
|
||||||
assign RepairD = WrongPredRetD | FlushedRetDE ;
|
assign RepairD = WrongPredRetD | FlushedRetDE ;
|
||||||
|
|
||||||
assign IncrRepairD = FlushedRetDE | (WrongPredRetD & ~InstrClassD[2]); // Guessed it was a ret, but its not
|
assign IncrRepairD = FlushedRetDE | (WrongPredRetD & ~RetD); // Guessed it was a ret, but its not
|
||||||
|
|
||||||
assign DecRepairD = WrongPredRetD & InstrClassD[2]; // Guessed non ret but is a ret.
|
assign DecRepairD = WrongPredRetD & RetD; // Guessed non ret but is a ret.
|
||||||
|
|
||||||
assign CounterEn = PopF | PushE | RepairD;
|
assign CounterEn = PopF | PushE | RepairD;
|
||||||
|
|
||||||
|
@ -103,29 +103,29 @@ module bpred (
|
|||||||
twoBitPredictor #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW,
|
twoBitPredictor #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW,
|
||||||
.FlushD, .FlushE, .FlushM, .FlushW,
|
.FlushD, .FlushE, .FlushM, .FlushW,
|
||||||
.PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
|
.PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
|
||||||
.BranchInstrE(BranchE), .BranchInstrM(BranchM), .PCSrcE);
|
.BranchE, .BranchM, .PCSrcE);
|
||||||
|
|
||||||
end else if (`BPRED_TYPE == "BP_GSHARE") begin:Predictor
|
end else if (`BPRED_TYPE == "BP_GSHARE") begin:Predictor
|
||||||
gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||||
.PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
|
.PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
|
||||||
.BranchInstrF(BPBranchF), .BranchInstrD(BranchD), .BranchInstrE(BranchE), .BranchInstrM(BranchM),
|
.BPBranchF, .BranchD, .BranchE, .BranchM,
|
||||||
.PCSrcE);
|
.PCSrcE);
|
||||||
|
|
||||||
end else if (`BPRED_TYPE == "BP_GLOBAL") begin:Predictor
|
end else if (`BPRED_TYPE == "BP_GLOBAL") begin:Predictor
|
||||||
gshare #(`BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
gshare #(`BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||||
.PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
|
.PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
|
||||||
.BranchInstrF(BPBranchF), .BranchInstrD(BranchD), .BranchInstrE(BranchE), .BranchInstrM(BranchM),
|
.BPBranchF, .BranchD, .BranchE, .BranchM,
|
||||||
.PCSrcE);
|
.PCSrcE);
|
||||||
|
|
||||||
end else if (`BPRED_TYPE == "BP_GSHARE_BASIC") begin:Predictor
|
end else if (`BPRED_TYPE == "BP_GSHARE_BASIC") begin:Predictor
|
||||||
gsharebasic #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
gsharebasic #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||||
.PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
|
.PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
|
||||||
.BranchInstrE(BranchE), .BranchInstrM(BranchM), .PCSrcE);
|
.BranchE, .BranchM, .PCSrcE);
|
||||||
|
|
||||||
end else if (`BPRED_TYPE == "BP_GLOBAL_BASIC") begin:Predictor
|
end else if (`BPRED_TYPE == "BP_GLOBAL_BASIC") begin:Predictor
|
||||||
gsharebasic #(`BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
gsharebasic #(`BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||||
.PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
|
.PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
|
||||||
.BranchInstrE(BranchE), .BranchInstrM(BranchM), .PCSrcE);
|
.BranchE, .BranchM, .PCSrcE);
|
||||||
|
|
||||||
end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor
|
end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor
|
||||||
// *** Fix me
|
// *** Fix me
|
||||||
@ -191,7 +191,7 @@ module bpred (
|
|||||||
|
|
||||||
// Part 3 RAS
|
// Part 3 RAS
|
||||||
RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
|
RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
|
||||||
.PredInstrClassF({BPJalF, BPRetF, BPJumpF, BPBranchF}), .InstrClassD({JalD, RetD, JumpD, BranchD}), .InstrClassE({JalE, RetE, JumpE, BranchE}),
|
.BPRetF, .RetD, .RetE, .JalE,
|
||||||
.WrongBPRetD, .RASPCF, .PCLinkE);
|
.WrongBPRetD, .RASPCF, .PCLinkE);
|
||||||
|
|
||||||
assign BPPredPCF = BPRetF ? RASPCF : BTAF;
|
assign BPPredPCF = BPRetF ? RASPCF : BTAF;
|
||||||
|
@ -39,7 +39,7 @@ module gshare #(parameter k = 10,
|
|||||||
output logic DirPredictionWrongE,
|
output logic DirPredictionWrongE,
|
||||||
// update
|
// update
|
||||||
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
|
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
|
||||||
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, PCSrcE
|
input logic BPBranchF, BranchD, BranchE, BranchM, PCSrcE
|
||||||
);
|
);
|
||||||
|
|
||||||
logic MatchF, MatchD, MatchE, MatchM;
|
logic MatchF, MatchD, MatchE, MatchM;
|
||||||
@ -68,10 +68,10 @@ module gshare #(parameter k = 10,
|
|||||||
assign IndexM = GHRM;
|
assign IndexM = GHRM;
|
||||||
end
|
end
|
||||||
|
|
||||||
assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF);
|
assign MatchF = BPBranchF & ~FlushD & (IndexNextF == IndexF);
|
||||||
assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD);
|
assign MatchD = BranchD & ~FlushE & (IndexNextF == IndexD);
|
||||||
assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE);
|
assign MatchE = BranchE & ~FlushM & (IndexNextF == IndexE);
|
||||||
assign MatchM = BranchInstrM & ~FlushW & (IndexNextF == IndexM);
|
assign MatchM = BranchM & ~FlushW & (IndexNextF == IndexM);
|
||||||
assign MatchNextX = MatchF | MatchD | MatchE | MatchM;
|
assign MatchNextX = MatchF | MatchD | MatchE | MatchM;
|
||||||
|
|
||||||
flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
|
flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
|
||||||
@ -91,7 +91,7 @@ module gshare #(parameter k = 10,
|
|||||||
.rd1(TableDirPredictionF),
|
.rd1(TableDirPredictionF),
|
||||||
.wa2(IndexM),
|
.wa2(IndexM),
|
||||||
.wd2(NewDirPredictionM),
|
.wd2(NewDirPredictionM),
|
||||||
.we2(BranchInstrM),
|
.we2(BranchM),
|
||||||
.bwe2(1'b1));
|
.bwe2(1'b1));
|
||||||
|
|
||||||
flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD);
|
flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD);
|
||||||
@ -100,16 +100,16 @@ module gshare #(parameter k = 10,
|
|||||||
satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
|
satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
|
||||||
flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewDirPredictionE, NewDirPredictionM);
|
flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewDirPredictionE, NewDirPredictionM);
|
||||||
|
|
||||||
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
|
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchE;
|
||||||
|
|
||||||
assign GHRNextF = BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : GHRF;
|
assign GHRNextF = BPBranchF ? {DirPredictionF[1], GHRF[k-1:1]} : GHRF;
|
||||||
assign GHRF = BranchInstrD ? {DirPredictionD[1], GHRD[k-1:1]} : GHRD;
|
assign GHRF = BranchD ? {DirPredictionD[1], GHRD[k-1:1]} : GHRD;
|
||||||
assign GHRD = BranchInstrE ? {PCSrcE, GHRE[k-1:1]} : GHRE;
|
assign GHRD = BranchE ? {PCSrcE, GHRE[k-1:1]} : GHRE;
|
||||||
assign GHRE = BranchInstrM ? {PCSrcM, GHRM[k-1:1]} : GHRM;
|
assign GHRE = BranchM ? {PCSrcM, GHRM[k-1:1]} : GHRM;
|
||||||
|
|
||||||
assign GHRNextM = {PCSrcM, GHRM[k-1:1]};
|
assign GHRNextM = {PCSrcM, GHRM[k-1:1]};
|
||||||
|
|
||||||
flopenr #(k) GHRReg(clk, reset, ~StallW & ~FlushW & BranchInstrM, GHRNextM, GHRM);
|
flopenr #(k) GHRReg(clk, reset, ~StallW & ~FlushW & BranchM, GHRNextM, GHRM);
|
||||||
flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
|
flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
@ -39,7 +39,7 @@ module gsharebasic #(parameter k = 10,
|
|||||||
output logic DirPredictionWrongE,
|
output logic DirPredictionWrongE,
|
||||||
// update
|
// update
|
||||||
input logic [`XLEN-1:0] PCNextF, PCM,
|
input logic [`XLEN-1:0] PCNextF, PCM,
|
||||||
input logic BranchInstrE, BranchInstrM, PCSrcE
|
input logic BranchE, BranchM, PCSrcE
|
||||||
);
|
);
|
||||||
|
|
||||||
logic [k-1:0] IndexNextF, IndexM;
|
logic [k-1:0] IndexNextF, IndexM;
|
||||||
@ -64,7 +64,7 @@ module gsharebasic #(parameter k = 10,
|
|||||||
.rd1(DirPredictionF),
|
.rd1(DirPredictionF),
|
||||||
.wa2(IndexM),
|
.wa2(IndexM),
|
||||||
.wd2(NewDirPredictionM),
|
.wd2(NewDirPredictionM),
|
||||||
.we2(BranchInstrM),
|
.we2(BranchM),
|
||||||
.bwe2(1'b1));
|
.bwe2(1'b1));
|
||||||
|
|
||||||
flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD);
|
flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD);
|
||||||
@ -73,10 +73,10 @@ module gsharebasic #(parameter k = 10,
|
|||||||
satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
|
satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
|
||||||
flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewDirPredictionE, NewDirPredictionM);
|
flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewDirPredictionE, NewDirPredictionM);
|
||||||
|
|
||||||
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
|
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchE;
|
||||||
|
|
||||||
assign GHRNext = BranchInstrM ? {PCSrcM, GHR[k-1:1]} : GHR;
|
assign GHRNext = BranchM ? {PCSrcM, GHR[k-1:1]} : GHR;
|
||||||
flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR);
|
flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchM, GHRNext, GHR);
|
||||||
flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
|
flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
|
||||||
|
|
||||||
flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
|
flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
|
||||||
|
@ -36,7 +36,7 @@ module twoBitPredictor #(parameter k = 10) (
|
|||||||
input logic [`XLEN-1:0] PCNextF, PCM,
|
input logic [`XLEN-1:0] PCNextF, PCM,
|
||||||
output logic [1:0] DirPredictionF,
|
output logic [1:0] DirPredictionF,
|
||||||
output logic DirPredictionWrongE,
|
output logic DirPredictionWrongE,
|
||||||
input logic BranchInstrE, BranchInstrM,
|
input logic BranchE, BranchM,
|
||||||
input logic PCSrcE
|
input logic PCSrcE
|
||||||
);
|
);
|
||||||
|
|
||||||
@ -60,13 +60,13 @@ module twoBitPredictor #(parameter k = 10) (
|
|||||||
.rd1(DirPredictionF),
|
.rd1(DirPredictionF),
|
||||||
.wa2(IndexM),
|
.wa2(IndexM),
|
||||||
.wd2(NewDirPredictionM),
|
.wd2(NewDirPredictionM),
|
||||||
.we2(BranchInstrM),
|
.we2(BranchM),
|
||||||
.bwe2(1'b1));
|
.bwe2(1'b1));
|
||||||
|
|
||||||
flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD);
|
flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD);
|
||||||
flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, DirPredictionD, DirPredictionE);
|
flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, DirPredictionD, DirPredictionE);
|
||||||
|
|
||||||
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
|
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchE;
|
||||||
|
|
||||||
satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
|
satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
|
||||||
flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewDirPredictionE, NewDirPredictionM);
|
flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewDirPredictionE, NewDirPredictionM);
|
||||||
|
Loading…
Reference in New Issue
Block a user