Merge pull request #247 from AlecVercruysse/code_quality

Code Quality
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Ross Thompson 2023-04-14 16:46:39 -05:00 committed by GitHub
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2
src/cache/cache.sv vendored
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@ -1,5 +1,5 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// cache // cache.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Ross Thompson ross1728@gmail.com
// Created: 7 July 2021 // Created: 7 July 2021

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@ -1,5 +1,5 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// dcache (data cache) // cacheLRU.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Ross Thompson ross1728@gmail.com
// Created: 20 July 2021 // Created: 20 July 2021

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@ -1,11 +1,11 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// dcache (data cache) fsm // cachefsm.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Ross Thompson ross1728@gmail.com
// Created: 25 August 2021 // Created: 25 August 2021
// Modified: 20 January 2023 // Modified: 20 January 2023
// //
// Purpose: Controller for the dcache fsm // Purpose: Controller for the cache fsm
// //
// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.14 and Table 7.1) // Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.14 and Table 7.1)
// //

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@ -1,11 +1,11 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// subcachelineread // subcachelineread.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Ross Thompson ross1728@gmail.com
// Created: 4 February 2022 // Created: 4 February 2022
// Modified: 20 January 2023 // Modified: 20 January 2023
// //
// Purpose: Muxes the cache line downto the word size. Also include possilbe save/restore registers/muxes. // Purpose: Muxes the cache line down to the word size. Also include possible save/restore registers/muxes.
// //
// Documentation: RISC-V System on Chip Design Chapter 7 // Documentation: RISC-V System on Chip Design Chapter 7
@ -31,7 +31,6 @@
module subcachelineread #(parameter LINELEN, WORDLEN, module subcachelineread #(parameter LINELEN, WORDLEN,
parameter MUXINTERVAL )( // The number of bits between mux. Set to 16 for I$ to support compressed. Set to `LLEN for D$ parameter MUXINTERVAL )( // The number of bits between mux. Set to 16 for I$ to support compressed. Set to `LLEN for D$
input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr, // Physical address input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr, // Physical address
input logic [LINELEN-1:0] ReadDataLine,// Read data of the whole cacheline input logic [LINELEN-1:0] ReadDataLine,// Read data of the whole cacheline
output logic [WORDLEN-1:0] ReadDataWord // read data of selected word. output logic [WORDLEN-1:0] ReadDataWord // read data of selected word.

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@ -51,11 +51,11 @@ module ahbcacheinterface #(
// cache interface // cache interface
input logic [`PA_BITS-1:0] CacheBusAdr, // Address of cache line input logic [`PA_BITS-1:0] CacheBusAdr, // Address of cache line
input logic [`LLEN-1:0] CacheReadDataWordM, // one word of cache line during a writeback input logic [`LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback
input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$ input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$
input logic Cacheable, // Memory operation is cachable input logic Cacheable, // Memory operation is cachable
input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch
output logic CacheBusAck, // Handshack to $ indicating bus transaction completed output logic CacheBusAck, // Handshake to $ indicating bus transaction completed
output logic [LINELEN-1:0] FetchBuffer, // Register to hold beats of cache line as the arrive from bus output logic [LINELEN-1:0] FetchBuffer, // Register to hold beats of cache line as the arrive from bus
output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase
output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr

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@ -1,5 +1,5 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// controller input stage // controllerinput.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Ross Thompson ross1728@gmail.com
// Created: August 31, 2022 // Created: August 31, 2022
@ -40,7 +40,7 @@ module controllerinput #(
input logic HRESETn, input logic HRESETn,
input logic Save, // Two or more managers requesting (HTRANS != 00) at the same time. Save the non-granted manager inputs input logic Save, // Two or more managers requesting (HTRANS != 00) at the same time. Save the non-granted manager inputs
input logic Restore, // Restore a saved manager inputs when it is finally granted input logic Restore, // Restore a saved manager inputs when it is finally granted
input logic Disable, // Supress HREADY to the non-granted manager input logic Disable, // Suppress HREADY to the non-granted manager
output logic Request, // This manager is making a request output logic Request, // This manager is making a request
// controller input // controller input
input logic [1:0] HTRANSIn, // Manager input. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ input logic [1:0] HTRANSIn, // Manager input. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
@ -48,14 +48,14 @@ module controllerinput #(
input logic [2:0] HSIZEIn, // Manager input. AHB transaction width input logic [2:0] HSIZEIn, // Manager input. AHB transaction width
input logic [2:0] HBURSTIn, // Manager input. AHB burst length input logic [2:0] HBURSTIn, // Manager input. AHB burst length
input logic [`PA_BITS-1:0] HADDRIn, // Manager input. AHB address input logic [`PA_BITS-1:0] HADDRIn, // Manager input. AHB address
output logic HREADYOut, // Indicate to manager the peripherial is not busy and another manager does not have priority output logic HREADYOut, // Indicate to manager the peripheral is not busy and another manager does not have priority
// controller output // controller output
output logic [1:0] HTRANSOut, // Aribrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ output logic [1:0] HTRANSOut, // Arbitrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
output logic HWRITEOut, // Aribrated manager transaction. AHB 0: Read operation 1: Write operation output logic HWRITEOut, // Arbitrated manager transaction. AHB 0: Read operation 1: Write operation
output logic [2:0] HSIZEOut, // Aribrated manager transaction. AHB transaction width output logic [2:0] HSIZEOut, // Arbitrated manager transaction. AHB transaction width
output logic [2:0] HBURSTOut, // Aribrated manager transaction. AHB burst length output logic [2:0] HBURSTOut, // Arbitrated manager transaction. AHB burst length
output logic [`PA_BITS-1:0] HADDROut, // Aribrated manager transaction. AHB address output logic [`PA_BITS-1:0] HADDROut, // Arbitrated manager transaction. AHB address
input logic HREADYIn // Peripherial ready input logic HREADYIn // Peripheral ready
); );
logic HWRITESave; logic HWRITESave;

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@ -1,5 +1,5 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// ebufsmarb // ebufsmarb.sv
// //
// Written: Ross Thompson ross1728@gmail.com // Written: Ross Thompson ross1728@gmail.com
// Created: 23 January 2023 // Created: 23 January 2023
@ -86,7 +86,7 @@ module ebufsmarb (
// Controller 1 (LSU) // Controller 1 (LSU)
// When both the IFU and LSU request at the same time, the FSM will go into the arbitrate state. // When both the IFU and LSU request at the same time, the FSM will go into the arbitrate state.
// Once the LSU request is done the fsm returns to IDLE. To prevent the LSU from regaining // Once the LSU request is done the fsm returns to IDLE. To prevent the LSU from regaining
// priority and re issuing the same memroy operation, the delayed IFUReqD squashes the LSU request. // priority and re-issuing the same memory operation, the delayed IFUReqD squashes the LSU request.
// This is necessary because the pipeline is stalled for the entire duration of both transactions, // This is necessary because the pipeline is stalled for the entire duration of both transactions,
// and the LSU memory request will stil be active. // and the LSU memory request will stil be active.
flopr #(1) ifureqreg(HCLK, ~HRESETn, IFUReq, IFUReqD); flopr #(1) ifureqreg(HCLK, ~HRESETn, IFUReq, IFUReqD);

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@ -1,5 +1,5 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// fdivsqrtpreproc.sv // fdivsqrtexpcalc.sv
// //
// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
// Modified:13 January 2022 // Modified:13 January 2022

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@ -1,5 +1,5 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// oneHotDecoder.sv // onehotdecoder.sv
// //
// Written: ross1728@gmail.com July 09, 2021 // Written: ross1728@gmail.com July 09, 2021
// Modified: // Modified:

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@ -187,7 +187,7 @@ module bpred (
// Correct branch/jump target. // Correct branch/jump target.
mux2 #(`XLEN) pccorrectemux(PCLinkE, IEUAdrE, PCSrcE, PCCorrectE); mux2 #(`XLEN) pccorrectemux(PCLinkE, IEUAdrE, PCSrcE, PCCorrectE);
// If the fence/csrw was predicted as a taken branch then we select PCF, rather PCE. // If the fence/csrw was predicted as a taken branch then we select PCF, rather than PCE.
// Effectively this is PCM+4 or the non-existant PCLinkM // Effectively this is PCM+4 or the non-existant PCLinkM
if(`INSTR_CLASS_PRED) mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPWrongM, NextValidPCE); if(`INSTR_CLASS_PRED) mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPWrongM, NextValidPCE);
else assign NextValidPCE = PCE; else assign NextValidPCE = PCE;
@ -201,7 +201,7 @@ module bpred (
// 3. target ras (ras target wrong / class[2]) // 3. target ras (ras target wrong / class[2])
// 4. direction (br dir wrong / class[0]) // 4. direction (br dir wrong / class[0])
// Unforuantely we can't use PCD to infer the correctness of the BTB or RAS because the class prediction // Unfortunately we can't use PCD to infer the correctness of the BTB or RAS because the class prediction
// could be wrong or the fall through address selected for branch predict not taken. // could be wrong or the fall through address selected for branch predict not taken.
// By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of
// both without the above inaccuracies. // both without the above inaccuracies.

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@ -1,7 +1,7 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// btb.sv // btb.sv
// //
// Written: Ross Thomposn ross1728@gmail.com // Written: Ross Thompson ross1728@gmail.com
// Created: February 15, 2021 // Created: February 15, 2021
// Modified: 24 January 2023 // Modified: 24 January 2023
// //
@ -73,7 +73,7 @@ module btb #(parameter Depth = 10 ) (
// must output a valid PC and valid bit during reset. Because only PCF, not PCNextF is reset, PCNextF is invalid // must output a valid PC and valid bit during reset. Because only PCF, not PCNextF is reset, PCNextF is invalid
// during reset. The BTB must produce a non X PC1NextF to allow the simulation to run. // during reset. The BTB must produce a non X PC1NextF to allow the simulation to run.
// While thie mux could be included in IFU it is not necessary for the IROM/I$/bus. // While the mux could be included in IFU it is not necessary for the IROM/I$/bus.
// For now it is optimal to leave it here. // For now it is optimal to leave it here.
assign ResetPC = `RESET_VECTOR; assign ResetPC = `RESET_VECTOR;
assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]};

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@ -169,7 +169,7 @@ module testbench;
logic InitializingMemories; logic InitializingMemories;
integer ResetCount, ResetThreshold; integer ResetCount, ResetThreshold;
logic InReset; logic InReset;
logic Begin; logic BeginSample;
// instantiate device to be tested // instantiate device to be tested
assign GPIOIN = 0; assign GPIOIN = 0;
@ -225,7 +225,8 @@ module testbench;
totalerrors = 0; totalerrors = 0;
testadr = 0; testadr = 0;
testadrNoBase = 0; testadrNoBase = 0;
// riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests and tests[0] == "2" refers to WallyRiscvArchTests // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests
// and tests[0] == "2" refers to WallyRiscvArchTests
riscofTest = tests[0] == "1" | tests[0] == "2"; riscofTest = tests[0] == "1" | tests[0] == "2";
// fill memory with defined values to reduce Xs in simulation // fill memory with defined values to reduce Xs in simulation
// Quick note the memory will need to be initialized. The C library does not // Quick note the memory will need to be initialized. The C library does not
@ -265,8 +266,9 @@ module testbench;
ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"}; ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"}; ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
end end
// declare memory labels that interest us, the updateProgramAddrLabelArray task will find the addr of each label and fill the array // declare memory labels that interest us, the updateProgramAddrLabelArray task will find
// to expand, add more elements to this array and initialize them to zero (also initilaize them to zero at the start of the next test) // the addr of each label and fill the array. To expand, add more elements to this array
// and initialize them to zero (also initilaize them to zero at the start of the next test)
if(!`FPGA) begin if(!`FPGA) begin
updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
$display("Read memfile %s", memfilename); $display("Read memfile %s", memfilename);
@ -311,8 +313,10 @@ module testbench;
#600; // give time for instructions in pipeline to finish #600; // give time for instructions in pipeline to finish
if (TEST == "embench") begin if (TEST == "embench") begin
// Writes contents of begin_signature to .sim.output file // Writes contents of begin_signature to .sim.output file
// this contains instret and cycles for start and end of test run, used by embench python speed script to calculate embench speed score // this contains instret and cycles for start and end of test run, used by embench
// also begin_signature contains the results of the self checking mechanism, which will be read by the python script for error checking // python speed script to calculate embench speed score.
// also, begin_signature contains the results of the self checking mechanism,
// which will be read by the python script for error checking
$display("Embench Benchmark: %s is done.", tests[test]); $display("Embench Benchmark: %s is done.", tests[test]);
if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"}; if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
else outputfile = {pathname, tests[test], ".sim.output"}; else outputfile = {pathname, tests[test], ".sim.output"};
@ -373,8 +377,7 @@ module testbench;
/* verilator lint_on INFINITELOOP */ /* verilator lint_on INFINITELOOP */
if (errors == 0) begin if (errors == 0) begin
$display("%s succeeded. Brilliant!!!", tests[test]); $display("%s succeeded. Brilliant!!!", tests[test]);
end end else begin
else begin
$display("%s failed with %d errors. :(", tests[test], errors); $display("%s failed with %d errors. :(", tests[test], errors);
totalerrors = totalerrors+1; totalerrors = totalerrors+1;
end end
@ -385,8 +388,7 @@ module testbench;
if (totalerrors == 0) $display("SUCCESS! All tests ran without failures."); if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
else $display("FAIL: %d test programs had errors", totalerrors); else $display("FAIL: %d test programs had errors", totalerrors);
$stop; $stop;
end end else begin
else begin
InitializingMemories = 1; InitializingMemories = 1;
// If there are still additional tests to run, read in information for the next test // If there are still additional tests to run, read in information for the next test
//pathname = tvpaths[tests[0]]; //pathname = tvpaths[tests[0]];
@ -480,10 +482,9 @@ module testbench;
assign EndSample = DCacheFlushStart & ~DCacheFlushDone; assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed); flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed);
assign Begin = StartSampleFirst & ~BeginDelayed; assign BeginSample = StartSampleFirst & ~BeginDelayed;
end end
always @(negedge clk) begin always @(negedge clk) begin
if(StartSample) begin if(StartSample) begin
for(HPMCindex = 0; HPMCindex < 32; HPMCindex += 1) begin for(HPMCindex = 0; HPMCindex < 32; HPMCindex += 1) begin
@ -559,7 +560,8 @@ end
int file; int file;
string LogFile; string LogFile;
logic resetD, resetEdge; logic resetD, resetEdge;
logic Enable, InvalDelayed; logic Enable;
logic InvalDelayed, InvalEdge;
assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn & assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn &
dut.core.ifu.immu.immu.pmachecker.Cacheable & dut.core.ifu.immu.immu.pmachecker.Cacheable &
@ -581,7 +583,7 @@ end
dut.core.ifu.bus.icache.icache.vict.cacheLRU.AllValid ? "E" : "M"; dut.core.ifu.bus.icache.icache.vict.cacheLRU.AllValid ? "E" : "M";
always @(posedge clk) begin always @(posedge clk) begin
if(resetEdge) $fwrite(file, "TRAIN\n"); if(resetEdge) $fwrite(file, "TRAIN\n");
if(Begin) $fwrite(file, "BEGIN %s\n", memfilename); if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename);
if(Enable) begin // only log i cache reads if(Enable) begin // only log i cache reads
$fwrite(file, "%h R %s\n", dut.core.ifu.PCPF, HitMissString); $fwrite(file, "%h R %s\n", dut.core.ifu.PCPF, HitMissString);
end end
@ -621,7 +623,7 @@ end
end end
always @(posedge clk) begin always @(posedge clk) begin
if(resetEdge) $fwrite(file, "TRAIN\n"); if(resetEdge) $fwrite(file, "TRAIN\n");
if(Begin) $fwrite(file, "BEGIN %s\n", memfilename); if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename);
if(Enabled) begin if(Enabled) begin
$fwrite(file, "%h %s %s\n", dut.core.lsu.PAdrM, AccessTypeString, HitMissString); $fwrite(file, "%h %s %s\n", dut.core.lsu.PAdrM, AccessTypeString, HitMissString);
end end
@ -656,7 +658,7 @@ end
end end
end end
// check for hange up. // check for hang up.
logic [`XLEN-1:0] OldPCW; logic [`XLEN-1:0] OldPCW;
integer WatchDogTimerCount; integer WatchDogTimerCount;
localparam WatchDogTimerThreshold = 1000000; localparam WatchDogTimerThreshold = 1000000;
@ -806,8 +808,7 @@ task automatic updateProgramAddrLabelArray;
integer returncode; integer returncode;
returncode = $fscanf(ProgramLabelMapFP, "%s\n", label); returncode = $fscanf(ProgramLabelMapFP, "%s\n", label);
returncode = $fscanf(ProgramAddrMapFP, "%s\n", adrstr); returncode = $fscanf(ProgramAddrMapFP, "%s\n", adrstr);
if (ProgramAddrLabelArray.exists(label)) if (ProgramAddrLabelArray.exists(label)) ProgramAddrLabelArray[label] = adrstr.atohex();
ProgramAddrLabelArray[label] = adrstr.atohex();
end end
end end
$fclose(ProgramLabelMapFP); $fclose(ProgramLabelMapFP);