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commented out lines to have divider work again

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This commit is contained in:
David Harris 2022-08-29 13:01:32 -07:00
parent 87b77658f2
commit 28db4fdc70
2 changed files with 21 additions and 5 deletions
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24
pipelined/src/fpu/fdivsqrtfsm.sv
View File

@ -66,7 +66,7 @@ module fdivsqrtfsm(
//logic [$clog2(`DIVLEN/2+3)-1:0] Dur;
logic [`DIVb+3:0] W;
logic SpecialCase;
logic WZeroDelayed; // *** later remove
logic WZeroDelayed, WZeroD; // *** later remove
//flopen #($clog2(`DIVLEN/2+3)) durflop(clk, DivStart, CalcDur, Dur);
assign DivBusy = (state == BUSY);
@ -83,13 +83,28 @@ module fdivsqrtfsm(
assign FSticky = SqrtM ? {FirstSM[`DIVb], FirstSM, 2'b0} | {FirstK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}};
// *** |... for continual -1 is not efficent fix - also only needed for radix-2
assign WZero = ((NextWSN^NextWCN)=={NextWSN[`DIVb+2:0]|NextWCN[`DIVb+2:0], 1'b0})|(((NextWSN+NextWCN+FZero)==0)&qn[`DIVCOPIES-1]);
assign DivSE = |W&~((W+FSticky)==0); //***not efficent fix == and need the & qn
assign DivSE = |W&~((W+FSticky)==0); //***not efficent fix == and need the & qn *** use next cycle
end else begin
assign WZero = ((NextWSN^NextWCN)=={NextWSN[`DIVb+2:0]|NextWCN[`DIVb+2:0], 1'b0});
assign DivSE = |W;
end
if (`RADIX == 2) begin
logic [`DIVb+3:0] FZero, FSticky;
logic [`DIVb+2:0] LastK, FirstK;
assign LastK = ({3'b111, LastC} & ~({3'b111, LastC} << 1));
assign FirstK = ({3'b111, FirstC<<1} & ~({3'b111, FirstC<<1} << 1));
assign FZero = SqrtM ? {LastSM[`DIVb], LastSM, 2'b0} | {LastK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}};
assign FSticky = SqrtM ? {FirstSM[`DIVb], FirstSM, 2'b0} | {FirstK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}};
// *** |... for continual -1 is not efficent fix - also only needed for radix-2
assign WZeroD = ((WS^WC)=={WS[`DIVb+2:0]|WC[`DIVb+2:0], 1'b0})|(((WS+WC+FZero)==0)&qn[`DIVCOPIES-1]);
end else begin
assign WZeroD = ((WS^WC)=={WS[`DIVb+2:0]|WC[`DIVb+2:0], 1'b0});
end
flopr #(1) WZeroReg(clk, reset | DivStart, WZero, WZeroDelayed);
assign DivDone = (state == DONE) | WZeroDelayed;
assign DivDone = (state == DONE);
// assign DivDone = (state == DONE) | (WZeroDelayed & (state == BUSY));
assign W = WC+WS;
assign NegSticky = W[`DIVb+3];
assign EarlyTermShiftE = step;
@ -108,7 +123,8 @@ module fdivsqrtfsm(
if (StallM) state <= #1 DONE;
else state <= #1 IDLE;
end else if (state == BUSY) begin
if (step == 0) begin
if (step == 1 | WZero ) begin
// if (step == 1 /* | WZero */) begin
state <= #1 DONE;
end
step <= step - 1;

2
pipelined/src/fpu/fdivsqrtpreproc.sv
View File

@ -73,7 +73,7 @@ module fdivsqrtpreproc (
assign SqrtX = Xe[0]^XZeroCnt[0] ? {1'b0, ~XZero, PreprocX} : {~XZero, PreprocX, 1'b0};
assign X = Sqrt ? {SqrtX, {`DIVb-1-`NF{1'b0}}} : {~XZero, PreprocX, {`DIVb-`NF{1'b0}}};
assign Dpreproc = {PreprocY, {`DIVN-1-`NF{1'b0}}};
assign Dur = (`DURLEN)'(`FPDUR-1);
assign Dur = (`DURLEN)'(`FPDUR);
// radix 2 radix 4
// 1 copies DIVLEN+2 DIVLEN+2/2