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Fixed the spurious AHB requests to address 0. Somehow by not having a default

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(else) in the fsm branch selection for STATE_READY in the d cache it was
possible to take an invalid branch through the fsm.
This commit is contained in:
Ross Thompson 2021-07-10 22:34:47 -05:00
parent d9fa3af94d
commit 282bde7205
1 changed files with 9 additions and 0 deletions
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9
wally-pipelined/src/cache/dcache.sv vendored
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@ -370,6 +370,7 @@ module dcache
// fsm state regs // fsm state regs
/* -----\/----- EXCLUDED -----\/-----
flopenl #(.TYPE(statetype)) flopenl #(.TYPE(statetype))
FSMReg(.clk(clk), FSMReg(.clk(clk),
.load(reset), .load(reset),
@ -377,6 +378,12 @@ module dcache
.val(STATE_READY), .val(STATE_READY),
.d(NextState), .d(NextState),
.q(CurrState)); .q(CurrState));
-----/\----- EXCLUDED -----/\----- */
always_ff @(posedge clk, posedge reset)
if (reset) CurrState <= #1 STATE_READY;
else CurrState <= #1 NextState;
// next state logic and some state ouputs. // next state logic and some state ouputs.
always_comb begin always_comb begin
@ -436,7 +443,9 @@ module dcache
else if(|MemRWM & FaultM & ~DTLBMissM) begin else if(|MemRWM & FaultM & ~DTLBMissM) begin
NextState = STATE_READY; NextState = STATE_READY;
end end
else NextState = STATE_READY;
end end
STATE_AMO_UPDATE: begin STATE_AMO_UPDATE: begin
NextState = STATE_AMO_WRITE; NextState = STATE_AMO_WRITE;
SaveSRAMRead = 1'b1; SaveSRAMRead = 1'b1;