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privileged comments
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David Harris
parent
496d343660
commit
27f81b09ce
@ -115,7 +115,7 @@ module csrsr (
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///////////////////////////////////////////
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if (`BIGENDIAN_SUPPORTED) begin: endianmux
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// determine whether bit endian accesses should be made
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// determine whether big endian accesses should be made
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logic [1:0] EndiannessPrivMode;
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always_comb begin
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if (SelHPTW) EndiannessPrivMode = `S_MODE;
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@ -27,59 +27,63 @@
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`include "wally-config.vh"
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// *** remove signals not needed by PMA/PMP now that it is moved
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module privileged (
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input logic clk, reset,
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input logic StallD, StallE, StallM, StallW,
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input logic FlushD, FlushE, FlushM, FlushW,
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(* mark_debug = "true" *) input logic CSRReadM, CSRWriteM,
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input logic [`XLEN-1:0] SrcAM,
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input logic [`XLEN-1:0] PCM, PCNext2F,
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input logic [31:0] InstrM,
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output logic [`XLEN-1:0] CSRReadValW,
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output logic [`XLEN-1:0] UnalignedPCNextF,
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output logic RetM, TrapM,
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output logic sfencevmaM,
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input logic InstrValidM, CommittedM, CommittedF,
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input logic FRegWriteM, LoadStallD,
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input logic DirPredictionWrongM,
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input logic BTBPredPCWrongM,
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input logic RASPredPCWrongM,
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input logic PredictionInstrClassWrongM,
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input logic [4:0] InstrClassM,
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input logic DCacheMiss,
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input logic DCacheAccess,
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input logic ICacheMiss,
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input logic ICacheAccess,
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input logic PrivilegedM,
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input logic HPTWInstrAccessFaultM,
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input logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM,
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input logic InstrMisalignedFaultM,
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input logic LoadMisalignedFaultM, StoreAmoMisalignedFaultM,
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input logic IllegalIEUInstrFaultD, IllegalFPUInstrM,
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input logic MTimerInt, MExtInt, SExtInt, MSwInt,
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input logic [63:0] MTIME_CLINT,
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input logic [`XLEN-1:0] IEUAdrM,
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input logic [4:0] SetFflagsM,
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// Trap signals from pmp/pma in mmu
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// *** do these need to be split up into one for dmem and one for ifu?
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// instead, could we only care about the instr and F pins that come from ifu and only care about the load/store and m pins that come from dmem?
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input logic InstrAccessFaultF,
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input logic LoadAccessFaultM,
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input logic StoreAmoAccessFaultM,
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input logic SelHPTW,
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output logic [1:0] PrivilegeModeW,
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output logic [`XLEN-1:0] SATP_REGW,
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output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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output logic [1:0] STATUS_MPP,
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output logic [1:0] STATUS_FS,
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output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
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output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
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output logic [2:0] FRM_REGW,
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output logic BreakpointFaultM, EcallFaultM, WFIStallM, BigEndianM
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// CSR Reads and Writes, and values needed for traps
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(* mark_debug = "true" *) input logic CSRReadM, CSRWriteM, // Read or write CSRs
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input logic [`XLEN-1:0] SrcAM, // GPR register to write
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input logic [31:0] InstrM, // Instruction
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input logic [`XLEN-1:0] IEUAdrM, // address from IEU
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input logic [`XLEN-1:0] PCM, PCNext2F, // program counter, next PC going to trap/return PC logic
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// control signals
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input logic InstrValidM, // Current instruction is valid (not flushed)
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input logic CommittedM, CommittedF, // current instruction is using bus; don't interrupt
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input logic PrivilegedM, // privileged instruction
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// processor events for performance counter logging
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input logic FRegWriteM, // instruction will write floating-point registers
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input logic LoadStallD, // load instruction is stalling
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input logic DirPredictionWrongM, // branch predictor guessed wrong directoin
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input logic BTBPredPCWrongM, // branch predictor guessed wrong target
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input logic RASPredPCWrongM, // return adddress stack guessed wrong target
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input logic PredictionInstrClassWrongM, // branch predictor guessed wrong instruction class
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input logic [4:0] InstrClassM, // actual instruction class
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input logic DCacheMiss, // data cache miss
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input logic DCacheAccess, // data cache accessed (hit or miss)
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input logic ICacheMiss, // instruction cache miss
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input logic ICacheAccess, // instruction cache access
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// fault sources
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input logic InstrAccessFaultF, // instruction access fault
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input logic LoadAccessFaultM, StoreAmoAccessFaultM, // load or store access fault
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input logic HPTWInstrAccessFaultM, // hardware page table access fault while fetching instruction PTE
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input logic InstrPageFaultF, // page faults
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input logic LoadPageFaultM, StoreAmoPageFaultM, // page faults
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input logic InstrMisalignedFaultM, // misaligned instruction fault
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input logic LoadMisalignedFaultM, StoreAmoMisalignedFaultM, // misaligned data fault
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input logic IllegalIEUInstrFaultD, IllegalFPUInstrM, // illegal instruction faults
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input logic MTimerInt, MExtInt, SExtInt, MSwInt, // interrupt sources
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input logic [63:0] MTIME_CLINT, // timer value from CLINT
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input logic [4:0] SetFflagsM, // set FCSR flags from FPU
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input logic SelHPTW, // HPTW in use. Causes system to use S-mode endianness for accesses
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// CSR outputs
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output logic [`XLEN-1:0] CSRReadValW, // Value read from CSR
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output logic [1:0] PrivilegeModeW, // current privilege mode
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output logic [`XLEN-1:0] SATP_REGW, // supervisor address translation register
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output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, // status register bits
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output logic [1:0] STATUS_MPP, STATUS_FS, // status register bits
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output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP configuration entries to MMU
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output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], // PMP address entries to MMU
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output logic [2:0] FRM_REGW, // FPU rounding mode
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// PC logic output in privileged unit
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output logic [`XLEN-1:0] UnalignedPCNextF, // Next PC from trap/return PC logic
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// control outputs
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output logic RetM, TrapM, // return instruction, or trap
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output logic sfencevmaM, // sfence.vma instruction
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output logic BigEndianM, // Use big endian in current privilege mode
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// Fault outputs
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output logic BreakpointFaultM, EcallFaultM, // breakpoint and Ecall traps should retire
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output logic WFIStallM // Stall in Memory stage for WFI until interrupt or timeout
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);
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logic [`LOG_XLEN-1:0] CauseM;
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