Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-02 09:45:18 +00:00
Code Issues Packages Projects Releases Wiki Activity

privileged comments

Browse Source
This commit is contained in:
David Harris 2023-01-13 17:57:38 -08:00
parent 496d343660
commit 27f81b09ce
2 changed files with 54 additions and 50 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
pipelined/src/privileged/csrsr.sv
View File

@ -115,7 +115,7 @@ module csrsr (
/////////////////////////////////////////// ///////////////////////////////////////////
if (`BIGENDIAN_SUPPORTED) begin: endianmux if (`BIGENDIAN_SUPPORTED) begin: endianmux
// determine whether bit endian accesses should be made // determine whether big endian accesses should be made
logic [1:0] EndiannessPrivMode; logic [1:0] EndiannessPrivMode;
always_comb begin always_comb begin
if (SelHPTW) EndiannessPrivMode = `S_MODE; if (SelHPTW) EndiannessPrivMode = `S_MODE;

102
pipelined/src/privileged/privileged.sv
View File

@ -27,59 +27,63 @@
`include "wally-config.vh" `include "wally-config.vh"
// *** remove signals not needed by PMA/PMP now that it is moved
module privileged ( module privileged (
input logic clk, reset, input logic clk, reset,
input logic StallD, StallE, StallM, StallW, input logic StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW, input logic FlushD, FlushE, FlushM, FlushW,
(* mark_debug = "true" *) input logic CSRReadM, CSRWriteM, // CSR Reads and Writes, and values needed for traps
input logic [`XLEN-1:0] SrcAM, (* mark_debug = "true" *) input logic CSRReadM, CSRWriteM, // Read or write CSRs
input logic [`XLEN-1:0] PCM, PCNext2F, input logic [`XLEN-1:0] SrcAM, // GPR register to write
input logic [31:0] InstrM, input logic [31:0] InstrM, // Instruction
output logic [`XLEN-1:0] CSRReadValW, input logic [`XLEN-1:0] IEUAdrM, // address from IEU
output logic [`XLEN-1:0] UnalignedPCNextF, input logic [`XLEN-1:0] PCM, PCNext2F, // program counter, next PC going to trap/return PC logic
output logic RetM, TrapM, // control signals
output logic sfencevmaM, input logic InstrValidM, // Current instruction is valid (not flushed)
input logic InstrValidM, CommittedM, CommittedF, input logic CommittedM, CommittedF, // current instruction is using bus; don't interrupt
input logic FRegWriteM, LoadStallD, input logic PrivilegedM, // privileged instruction
input logic DirPredictionWrongM, // processor events for performance counter logging
input logic BTBPredPCWrongM, input logic FRegWriteM, // instruction will write floating-point registers
input logic RASPredPCWrongM, input logic LoadStallD, // load instruction is stalling
input logic PredictionInstrClassWrongM, input logic DirPredictionWrongM, // branch predictor guessed wrong directoin
input logic [4:0] InstrClassM, input logic BTBPredPCWrongM, // branch predictor guessed wrong target
input logic DCacheMiss, input logic RASPredPCWrongM, // return adddress stack guessed wrong target
input logic DCacheAccess, input logic PredictionInstrClassWrongM, // branch predictor guessed wrong instruction class
input logic ICacheMiss, input logic [4:0] InstrClassM, // actual instruction class
input logic ICacheAccess, input logic DCacheMiss, // data cache miss
input logic PrivilegedM, input logic DCacheAccess, // data cache accessed (hit or miss)
input logic HPTWInstrAccessFaultM, input logic ICacheMiss, // instruction cache miss
input logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM, input logic ICacheAccess, // instruction cache access
input logic InstrMisalignedFaultM, // fault sources
input logic LoadMisalignedFaultM, StoreAmoMisalignedFaultM, input logic InstrAccessFaultF, // instruction access fault
input logic IllegalIEUInstrFaultD, IllegalFPUInstrM, input logic LoadAccessFaultM, StoreAmoAccessFaultM, // load or store access fault
input logic MTimerInt, MExtInt, SExtInt, MSwInt, input logic HPTWInstrAccessFaultM, // hardware page table access fault while fetching instruction PTE
input logic [63:0] MTIME_CLINT, input logic InstrPageFaultF, // page faults
input logic [`XLEN-1:0] IEUAdrM, input logic LoadPageFaultM, StoreAmoPageFaultM, // page faults
input logic [4:0] SetFflagsM, input logic InstrMisalignedFaultM, // misaligned instruction fault
input logic LoadMisalignedFaultM, StoreAmoMisalignedFaultM, // misaligned data fault
// Trap signals from pmp/pma in mmu input logic IllegalIEUInstrFaultD, IllegalFPUInstrM, // illegal instruction faults
// *** do these need to be split up into one for dmem and one for ifu? input logic MTimerInt, MExtInt, SExtInt, MSwInt, // interrupt sources
// instead, could we only care about the instr and F pins that come from ifu and only care about the load/store and m pins that come from dmem? input logic [63:0] MTIME_CLINT, // timer value from CLINT
input logic [4:0] SetFflagsM, // set FCSR flags from FPU
input logic InstrAccessFaultF, input logic SelHPTW, // HPTW in use. Causes system to use S-mode endianness for accesses
input logic LoadAccessFaultM, // CSR outputs
input logic StoreAmoAccessFaultM, output logic [`XLEN-1:0] CSRReadValW, // Value read from CSR
input logic SelHPTW, output logic [1:0] PrivilegeModeW, // current privilege mode
output logic [`XLEN-1:0] SATP_REGW, // supervisor address translation register
output logic [1:0] PrivilegeModeW, output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, // status register bits
output logic [`XLEN-1:0] SATP_REGW, output logic [1:0] STATUS_MPP, STATUS_FS, // status register bits
output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP configuration entries to MMU
output logic [1:0] STATUS_MPP, output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], // PMP address entries to MMU
output logic [1:0] STATUS_FS, output logic [2:0] FRM_REGW, // FPU rounding mode
output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], // PC logic output in privileged unit
output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], output logic [`XLEN-1:0] UnalignedPCNextF, // Next PC from trap/return PC logic
output logic [2:0] FRM_REGW, // control outputs
output logic BreakpointFaultM, EcallFaultM, WFIStallM, BigEndianM output logic RetM, TrapM, // return instruction, or trap
output logic sfencevmaM, // sfence.vma instruction
output logic BigEndianM, // Use big endian in current privilege mode
// Fault outputs
output logic BreakpointFaultM, EcallFaultM, // breakpoint and Ecall traps should retire
output logic WFIStallM // Stall in Memory stage for WFI until interrupt or timeout
); );
logic [`LOG_XLEN-1:0] CauseM; logic [`LOG_XLEN-1:0] CauseM;