diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 741044dae..dbb69e464 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -79,7 +79,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER logic ClearValid; logic ClearDirty; logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0]; - logic [NUMWAYS-1:0] HitWay, HitWaySaved, HitWayFinal; + logic [NUMWAYS-1:0] HitWay; logic CacheHit; logic SetDirty; logic SetValid; @@ -107,7 +107,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER logic [1:0] CacheRW, CacheAtomic; logic [LINELEN-1:0] ReadDataLine, ReadDataLineCache; logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr; - logic save, restore; logic SelBusBuffer; logic SRAMEnable; @@ -134,7 +133,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER .Invalidate(InvalidateCacheM)); if(NUMWAYS > 1) begin:vict cachereplacementpolicy #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy( - .clk, .reset, .HitWay(HitWayFinal), .VictimWay, .RAdr, .LRUWriteEn); + .clk, .reset, .HitWay, .VictimWay, .RAdr, .LRUWriteEn); end else assign VictimWay = 1'b1; // one hot. assign CacheHit = | HitWay; assign VictimDirty = | VictimDirtyWay; @@ -144,15 +143,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWay), .y(ReadDataLineCache)); or_rows #(NUMWAYS, TAGLEN) VictimTagAOMux(.a(VictimTagWay), .y(VictimTag)); - // Because of the sram clocked read when the ieu is stalled the read data maybe lost. - // There are two ways to resolve. 1. We can replay the read of the sram or we can save - // the data. Replay is eaiser but creates a longer critical path. - // save/restore only wayhit and readdata. - if(!`REPLAY) begin - flopenr #(NUMWAYS) wayhitsavereg(clk, save, reset, HitWay, HitWaySaved); - mux2 #(NUMWAYS) saverestoremux(HitWay, HitWaySaved, restore, HitWayFinal); - end else assign HitWayFinal = HitWay; - // like to fix this. if(DCACHE) mux2 #(LOGWPL) WordAdrrMux(.d0(PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]), @@ -163,7 +153,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER mux2 #(LINELEN) EarlyReturnBuf(ReadDataLineCache, CacheBusWriteData, SelBusBuffer, ReadDataLine); subcachelineread #(LINELEN, WORDLEN, MUXINTERVAL, LOGWPL) subcachelineread( - .clk, .reset, .PAdr(WordOffsetAddr), .save, .restore, + .PAdr(WordOffsetAddr), .ReadDataLine, .ReadDataWord); ///////////////////////////////////////////////////////////////////////////////////////////// @@ -210,7 +200,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path: Write Enables ///////////////////////////////////////////////////////////////////////////////////////////// - mux3 #(NUMWAYS) selectwaymux(HitWayFinal, VictimWay, FlushWay, + mux3 #(NUMWAYS) selectwaymux(HitWay, VictimWay, FlushWay, {SelFlush, SetValid}, SelectedWay); assign SetValidWay = SetValid ? SelectedWay : '0; assign ClearValidWay = ClearValid ? SelectedWay : '0; @@ -231,6 +221,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER .FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst, .FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelBusBuffer, .InvalidateCache(InvalidateCacheM), - .save, .restore, .SRAMEnable, + .SRAMEnable, .LRUWriteEn); endmodule diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 84c47b1c1..46f7825b6 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -76,8 +76,6 @@ module cachefsm output logic FlushAdrCntRst, output logic FlushWayCntRst, output logic SelBusBuffer, - output logic save, - output logic restore, output logic SRAMEnable); logic resetDelay; @@ -198,10 +196,6 @@ module cachefsm assign CacheFetchLine = (CurrState == STATE_READY & DoAnyMiss); assign CacheWriteLine = (CurrState == STATE_MISS_EVICT_DIRTY_START) | (CurrState == STATE_FLUSH_CHECK & VictimDirty); - // handle cpu stall. - assign restore = '0; - assign save = '0; - // **** can this be simplified? assign SelAdr = (CurrState == STATE_READY & (IgnoreRequestTLB & ~TrapM)) | // Ignore Request is needed on TLB miss. // use the raw requests as we don't want IgnoreRequestTrapM in the critical path diff --git a/pipelined/src/cache/subcachelineread.sv b/pipelined/src/cache/subcachelineread.sv index 2a3395ea5..fe9139659 100644 --- a/pipelined/src/cache/subcachelineread.sv +++ b/pipelined/src/cache/subcachelineread.sv @@ -31,10 +31,7 @@ `include "wally-config.vh" module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL, LOGWPL)( - input logic clk, - input logic reset, input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr, - input logic save, restore, input logic [LINELEN-1:0] ReadDataLine, output logic [WORDLEN-1:0] ReadDataWord); @@ -43,7 +40,6 @@ module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL, LOGWPL)( localparam PADLEN = WORDLEN-MUXINTERVAL; logic [LINELEN+(WORDLEN-MUXINTERVAL)-1:0] ReadDataLinePad; logic [WORDLEN-1:0] ReadDataLineSets [(LINELEN/MUXINTERVAL)-1:0]; - logic [WORDLEN-1:0] ReadDataWordRaw, ReadDataWordSaved; if (PADLEN > 0) begin logic [PADLEN-1:0] Pad; @@ -56,11 +52,5 @@ module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL, LOGWPL)( assign ReadDataLineSets[index] = ReadDataLinePad[(index*MUXINTERVAL)+WORDLEN-1: (index*MUXINTERVAL)]; end // variable input mux - // *** maybe remove REPLAY config later after deciding which way is best - assign ReadDataWordRaw = ReadDataLineSets[PAdr]; - if(!`REPLAY) begin - flopen #(WORDLEN) cachereaddatasavereg(clk, save, ReadDataWordRaw, ReadDataWordSaved); - mux2 #(WORDLEN) readdatasaverestoremux(ReadDataWordRaw, ReadDataWordSaved, - restore, ReadDataWord); - end else assign ReadDataWord = ReadDataWordRaw; + assign ReadDataWord = ReadDataLineSets[PAdr]; endmodule