diff --git a/pipelined/regression/wave-fpu.do b/pipelined/regression/wave-fpu.do index f06fb6d63..7669c0213 100644 --- a/pipelined/regression/wave-fpu.do +++ b/pipelined/regression/wave-fpu.do @@ -9,7 +9,7 @@ add wave -noupdate /testbenchfp/Res add wave -noupdate /testbenchfp/Ans add wave -noupdate /testbenchfp/DivStart add wave -noupdate /testbenchfp/DivBusy -add wave -noupdate /testbenchfp/divsqrt/srtfsm/state +add wave -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtfsm/state add wave -group {PostProc} -noupdate /testbenchfp/postprocess/* add wave -group {PostProc} -noupdate /testbenchfp/postprocess/specialcase/* add wave -group {PostProc} -noupdate /testbenchfp/postprocess/flags/* @@ -20,21 +20,21 @@ add wave -group {PostProc} -noupdate /testbenchfp/postprocess/round/* add wave -group {PostProc} -noupdate /testbenchfp/postprocess/fmashiftcalc/* add wave -group {PostProc} -noupdate /testbenchfp/postprocess/divshiftcalc/* add wave -group {PostProc} -noupdate /testbenchfp/postprocess/cvtshiftcalc/* -add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/WC -add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/WS -add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/WCA -add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/WSA -add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/Q -add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/QM -add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/QNext -add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/QMNext -add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/* -add wave -group {Divide} -group inter0 -noupdate /testbenchfp/divsqrt/srt/interations[0]/divinteration/* -add wave -group {Divide} -group inter0 -noupdate /testbenchfp/divsqrt/srt/interations[0]/divinteration/otfc/otfc2/* -add wave -group {Divide} -group inter0 -noupdate /testbenchfp/divsqrt/srt/interations[0]/divinteration/qsel/qsel2/* -# add wave -group {Divide} -group inter0 -noupdate /testbenchfp/divsqrt/srt/interations[0]/divinteration/genblk1/qsel4/* -add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srtpreproc/* -add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srtpreproc/expcalc/* -add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srtfsm/* +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/WC +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/WS +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/WCA +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/WSA +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/Q +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/QM +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/QNext +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/QMNext +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/* +add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/divinteration/* +add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/divinteration/otfc/otfc2/* +add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/divinteration/qsel/qsel2/* +# add wave -group {Divide} -group inter0 -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtiter/interations[0]/divinteration/genblk1/qsel4/* +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtpreproc/* +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtpreproc/expcalc/* +add wave -group {Divide} -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtfsm/* add wave -group {Testbench} -noupdate /testbenchfp/* add wave -group {Testbench} -noupdate /testbenchfp/readvectors/* diff --git a/pipelined/src/fpu/divsqrt.sv b/pipelined/src/fpu/fdivsqrt.sv similarity index 79% rename from pipelined/src/fpu/divsqrt.sv rename to pipelined/src/fpu/fdivsqrt.sv index e76d86451..794dd7526 100644 --- a/pipelined/src/fpu/divsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// srt.sv +// fdivsqrt.sv // // Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek // Modified:13 January 2022 @@ -30,7 +30,7 @@ `include "wally-config.vh" -module divsqrt( +module fdivsqrt( input logic clk, input logic reset, input logic [`FMTBITS-1:0] FmtE, @@ -67,10 +67,10 @@ module divsqrt( logic NegSticky; logic [`DIVCOPIES-1:0] qn; - srtpreproc srtpreproc(.clk, .DivStart(DivStartE), .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), .Sqrt(SqrtE), .Dur, .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc); + fdivsqrtpreproc fdivsqrtpreproc(.clk, .DivStart(DivStartE), .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), .Sqrt(SqrtE), .Dur, .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc); - srtfsm srtfsm(.reset, .qn, .LastSM, .LastC, .FirstSM, .FirstC, .D, .XsE, .SqrtE, .SqrtM, .NextWSN, .NextWCN, .WS, .WC, .Dur, .DivBusy, .clk, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, .DivSE(DivSM), .XNaNE, .YNaNE, + fdivsqrtfsm fdivsqrtfsm(.reset, .qn, .LastSM, .LastC, .FirstSM, .FirstC, .D, .XsE, .SqrtE, .SqrtM, .NextWSN, .NextWCN, .WS, .WC, .Dur, .DivBusy, .clk, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, .DivSE(DivSM), .XNaNE, .YNaNE, .StickyWSA, .XInfE, .YInfE, .NegSticky(NegSticky), .EarlyTermShiftE(EarlyTermShiftM)); - srt srt(.clk, .qn, .D, .LastSM, .LastC, .FirstSM, .FirstC, .SqrtE, .SqrtM, .X,.Dpreproc, .NegSticky, .FirstWS(WS), .FirstWC(WC), .NextWSN, .NextWCN, .DivStart(DivStartE), .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE, + fdivsqrtiter fdivsqrtiter(.clk, .qn, .D, .LastSM, .LastC, .FirstSM, .FirstC, .SqrtE, .SqrtM, .X,.Dpreproc, .NegSticky, .FirstWS(WS), .FirstWC(WC), .NextWSN, .NextWCN, .DivStart(DivStartE), .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE, .StickyWSA, .DivBusy, .Qm(QmM)); endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/srtfsm.sv b/pipelined/src/fpu/fdivsqrtfsm.sv similarity index 98% rename from pipelined/src/fpu/srtfsm.sv rename to pipelined/src/fpu/fdivsqrtfsm.sv index 0e6ec51af..52cc6b757 100644 --- a/pipelined/src/fpu/srtfsm.sv +++ b/pipelined/src/fpu/fdivsqrtfsm.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// srt.sv +// fdivsqrtfsm.sv // // Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek // Modified:13 January 2022 @@ -30,7 +30,7 @@ `include "wally-config.vh" -module srtfsm( +module fdivsqrtfsm( input logic clk, input logic reset, input logic [`DIVb+3:0] NextWSN, NextWCN, WS, WC, diff --git a/pipelined/src/fpu/srt.sv b/pipelined/src/fpu/fdivsqrtiter.sv similarity index 99% rename from pipelined/src/fpu/srt.sv rename to pipelined/src/fpu/fdivsqrtiter.sv index a9b584130..daae52ccc 100644 --- a/pipelined/src/fpu/srt.sv +++ b/pipelined/src/fpu/fdivsqrtiter.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// srt.sv +// fdivsqrtiter.sv // // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu // Modified:13 January 2022 @@ -30,7 +30,7 @@ `include "wally-config.vh" -module srt( +module fdivsqrtiter( input logic clk, input logic DivStart, input logic DivBusy, diff --git a/pipelined/src/fpu/srtpreproc.sv b/pipelined/src/fpu/fdivsqrtpreproc.sv similarity index 98% rename from pipelined/src/fpu/srtpreproc.sv rename to pipelined/src/fpu/fdivsqrtpreproc.sv index 63b2b9779..0338c2b83 100644 --- a/pipelined/src/fpu/srtpreproc.sv +++ b/pipelined/src/fpu/fdivsqrtpreproc.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// srt.sv +// fdivsqrtpreproc.sv // // Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek // Modified:13 January 2022 @@ -30,7 +30,7 @@ `include "wally-config.vh" -module srtpreproc ( +module fdivsqrtpreproc ( input logic clk, input logic DivStart, input logic [`NF:0] Xm, Ym, diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index fe69bb081..bfc6af0e6 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -257,7 +257,7 @@ module fpu ( // - fdiv // - fsqrt // *** add other opperations - divsqrt divsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]), + fdivsqrt fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]), .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .DivStartE(DivStartE), .XsE, .StallE, .StallM, .DivSM, .DivBusy(FDivBusyE), .QeM, //***change divbusyE to M signal .EarlyTermShiftM, .QmM, .DivDone(DivDoneM)); diff --git a/pipelined/testbench/testbench-fp.sv b/pipelined/testbench/testbench-fp.sv index 88190aad2..2a5e6b4ff 100644 --- a/pipelined/testbench/testbench-fp.sv +++ b/pipelined/testbench/testbench-fp.sv @@ -669,12 +669,14 @@ module testbenchfp; /////////////////////////////////////////////////////////////////////////////////////////////// // instantiate devices under test - fma fma(.Xs(Xs), .Ys(Ys), .Zs(Zs), - .Xe(Xe), .Ye(Ye), .Ze(Ze), - .Xm(Xm), .Ym(Ym), .Zm(Zm), - .XZero, .YZero, .ZZero, .Ss, .Se, - .OpCtrl(OpCtrlVal), .Fmt(ModFmt), .Sm, .NegSum, .InvA, .SCnt, .As, .Ps, - .Pe, .ZmSticky, .KillProd); + if (TEST === "fma"| TEST === "mul" | TEST === "add" | TEST === "all") begin : fma + fma fma(.Xs(Xs), .Ys(Ys), .Zs(Zs), + .Xe(Xe), .Ye(Ye), .Ze(Ze), + .Xm(Xm), .Ym(Ym), .Zm(Zm), + .XZero, .YZero, .ZZero, .Ss, .Se, + .OpCtrl(OpCtrlVal), .Fmt(ModFmt), .Sm, .NegSum, .InvA, .SCnt, .As, .Ps, + .Pe, .ZmSticky, .KillProd); + end postprocess postprocess(.Xs(Xs), .Ys(Ys), .PostProcSel(UnitVal[1:0]), .Ze(Ze), .ZDenorm(ZDenorm), .OpCtrl(OpCtrlVal), .DivQm(Quot), .DivQe(DivCalcExp), @@ -687,16 +689,23 @@ module testbenchfp; .FmaSm(Sm), .FmaNegSum(NegSum), .FmaInvA(InvA), .FmaSCnt(SCnt), .DivEarlyTermShift(EarlyTermShift), .FmaAs(As), .FmaPs(Ps), .Fmt(ModFmt), .Frm(FrmVal), .PostProcFlg(Flg), .PostProcRes(FpRes), .FCvtIntRes(IntRes)); - fcvt fcvt (.Xs(Xs), .Xe(Xe), .Xm(Xm), .Int(SrcA), .ToInt(WriteIntVal), - .XZero(XZero), .XDenorm(XDenorm), .OpCtrl(OpCtrlVal), .IntZero, - .Fmt(ModFmt), .Ce(CvtCalcExpE), .ShiftAmt(CvtShiftAmtE), .ResDenormUf(CvtResDenormUfE), .Cs(CvtResSgnE), .LzcIn(CvtLzcInE)); - fcmp fcmp (.Fmt(ModFmt), .OpCtrl(OpCtrlVal), .Xs, .Ys, .Xe, .Ye, - .Xm, .Ym, .XZero, .YZero, .CmpIntRes(CmpRes), - .XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes)); - divsqrt divsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]), - .XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), .XNaNE(XNaN), .YNaNE(YNaN), .DivStartE(DivStart), - .StallE(1'b0), .StallM(1'b0), .DivSM(DivSticky), .DivBusy, .QeM(DivCalcExp), - .EarlyTermShiftM(EarlyTermShift), .QmM(Quot), .DivDone); + if (TEST === "cvtfp" | TEST === "cvtint" | TEST === "all") begin : fcvt + fcvt fcvt (.Xs(Xs), .Xe(Xe), .Xm(Xm), .Int(SrcA), .ToInt(WriteIntVal), + .XZero(XZero), .XDenorm(XDenorm), .OpCtrl(OpCtrlVal), .IntZero, + .Fmt(ModFmt), .Ce(CvtCalcExpE), .ShiftAmt(CvtShiftAmtE), .ResDenormUf(CvtResDenormUfE), .Cs(CvtResSgnE), .LzcIn(CvtLzcInE)); + end + + if (TEST === "cmp" | TEST === "all") begin: fcmp + fcmp fcmp (.Fmt(ModFmt), .OpCtrl(OpCtrlVal), .Xs, .Ys, .Xe, .Ye, + .Xm, .Ym, .XZero, .YZero, .CmpIntRes(CmpRes), + .XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes)); + end + if (TEST === "div" | TEST === "sqrt" | TEST === "all") begin: fdivsqrt + fdivsqrt fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]), + .XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), .XNaNE(XNaN), .YNaNE(YNaN), .DivStartE(DivStart), + .StallE(1'b0), .StallM(1'b0), .DivSM(DivSticky), .DivBusy, .QeM(DivCalcExp), + .EarlyTermShiftM(EarlyTermShift), .QmM(Quot), .DivDone); + end assign CmpFlg[3:0] = 0;