From 9e93f21990b592a7748c227fdd8e7f20a6534872 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 19 Jun 2024 15:13:49 -0700
Subject: [PATCH] Updated covergen to not include stores as they are
 incomplete. Modified makefile riscv-dv to not simulation only generate tests.

---
 Makefile                  |  4 +--
 bin/imperas-one-time.sh   | 55 ---------------------------------------
 tests/testgen/covergen.py |  4 +--
 3 files changed, 4 insertions(+), 59 deletions(-)
 delete mode 100755 bin/imperas-one-time.sh

diff --git a/Makefile b/Makefile
index b78bb689d..740287dcc 100644
--- a/Makefile
+++ b/Makefile
@@ -55,8 +55,8 @@ riscvdv:
 #	python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv  --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gcc_compile	>> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1
 #	python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv  --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps iss_sim		>> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1
 #	run-elf.bash --seed ${SIM}/questa/seed0.txt --verbose --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o													>> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1
-	run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/riscv.ucdb --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o								>> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1
-	cp ${SIM}/questa/riscv.ucdb ${SIM}/questa/functcov_ucdbs/${test_name}.ucdb
+	#run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/riscv.ucdb --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o								>> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1
+	#cp ${SIM}/questa/riscv.ucdb ${SIM}/questa/functcov_ucdbs/${test_name}.ucdb
 
 riscvdv_functcov:
 	mkdir -p ${SIM}/questa/functcov_logs
diff --git a/bin/imperas-one-time.sh b/bin/imperas-one-time.sh
deleted file mode 100755
index 339b4c74f..000000000
--- a/bin/imperas-one-time.sh
+++ /dev/null
@@ -1,55 +0,0 @@
-#!/bin/bash
-###########################################
-## imperas-one-time.sh
-##
-## Written: Ross Thompson (ross1728@gmail.com) and Lee Moore (moore@imperas.com)
-## Created: 31 January 2023
-## Modified: 31 January 2023
-##
-## Purpose: One time setup script for running imperas.
-## 
-## A component of the CORE-V-WALLY configurable RISC-V project.
-## https://github.com/openhwgroup/cvw
-## 
-## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-##
-## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-##
-## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-## may obtain a copy of the License at
-##
-## https://solderpad.org/licenses/SHL-2.1/
-##
-## Unless required by applicable law or agreed to in writing, any work distributed under the 
-## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-## either express or implied. See the License for the specific language governing permissions 
-## and limitations under the License.
-################################################################################################
-
-
-IMP_HASH=355a055ff7e36bc897e942e41f06e1baf96e34d5
-
-# clone the Imperas repo
-cd $WALY
-if [ ! -d external ]; then
-    mkdir -p external
-fi
-pushd external
-    if [ ! -d ImperasDV-HMC ]; then
-	git clone git@github.com:Imperas/ImperasDV-HMC.git
-    fi
-    pushd ImperasDV-HMC
-    git checkout $IMP_HASH
-    popd
-popd
-
-# Setup Imperas
-source ${WALLY}/external/ImperasDV-HMC/Imperas/bin/setup.sh
-setupImperas ${WALLY}/external/ImperasDV-HMC/Imperas
-export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC
-
-# setup QUESTA (Imperas only command, YMMV)
-#svsetup -questa
-
-
diff --git a/tests/testgen/covergen.py b/tests/testgen/covergen.py
index 5a01b7c62..1e06e7b9c 100755
--- a/tests/testgen/covergen.py
+++ b/tests/testgen/covergen.py
@@ -60,8 +60,8 @@ def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, stor
     lines = lines + test + " x" + str(rd) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation \n"
   elif (test in stypes):#["sb", "sh", "sw", "sd"]
     #lines = lines + test + " x" + str(rs2) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation \n"
-    lines = lines + test + " x" + str(rs2) + ", " "0(x" + str(rs1) + ") # perform operation \n"
-    #print("Error: %s type not implemented yet" % test)
+    #lines = lines + test + " x" + str(rs2) + ", " "0(x" + str(rs1) + ") # perform operation \n"
+    print("Error: %s type not implemented yet" % test)
   elif (test in btypes):#["beq", "bne", "blt", "bge", "bltu", "bgeu"]
     if (randint(1,100) > 50):
       rs1val = rs2val