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Update fregfile.sv

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Program clean up
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Harshini Srinath 2023-06-11 16:49:20 -07:00 committed by GitHub
parent 7770f7e79b
commit 2739ea26a7
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1 changed files with 2 additions and 3 deletions
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src/fpu/fregfile.sv
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@ -30,8 +30,8 @@ module fregfile #(parameter FLEN) (
input logic clk, reset, input logic clk, reset,
input logic we4, // write enable input logic we4, // write enable
input logic [4:0] a1, a2, a3, a4, // adresses input logic [4:0] a1, a2, a3, a4, // adresses
input logic [FLEN-1:0] wd4, // write data input logic [FLEN-1:0] wd4, // write data
output logic [FLEN-1:0] rd1, rd2, rd3 // read data output logic [FLEN-1:0] rd1, rd2, rd3 // read data
); );
logic [FLEN-1:0] rf[31:0]; logic [FLEN-1:0] rf[31:0];
@ -51,4 +51,3 @@ module fregfile #(parameter FLEN) (
assign #2 rd3 = rf[a3]; assign #2 rd3 = rf[a3];
endmodule // regfile endmodule // regfile