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Removed .* from CSRs

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This commit is contained in:
David Harris 2021-12-31 07:11:03 +00:00
parent ae3767bd54
commit 272e884581
2 changed files with 43 additions and 9 deletions
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50
wally-pipelined/src/privileged/csr.sv
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@ -112,13 +112,49 @@ module csr #(parameter
assign CSRSWriteM = CSRWriteM && (|PrivilegeModeW); assign CSRSWriteM = CSRWriteM && (|PrivilegeModeW);
assign CSRUWriteM = CSRWriteM; assign CSRUWriteM = CSRWriteM;
csri csri(.*); csri csri(.clk, .reset, .StallW, .CSRMWriteM, .CSRSWriteM,
csrsr csrsr(.*); .CSRAdrM, .ExtIntM, .TimerIntM, .SwIntM,
csrc counters(.*); .MIDELEG_REGW, .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .CSRWriteValM);
csrm csrm(.*); // Machine Mode CSRs csrsr csrsr(.clk, .reset, .StallW,
csrs csrs(.*); .WriteMSTATUSM, .WriteSSTATUSM, .WriteUSTATUSM,
csrn csrn(.CSRNWriteM(CSRUWriteM), .*); // User Mode Exception Registers .TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW,
csru csru(.*); // Floating Point Flags are part of User MOde .mretM, .sretM, .uretM, .WriteFRMM, .WriteFFLAGSM, .CSRWriteValM,
.MSTATUS_REGW, .SSTATUS_REGW, .USTATUS_REGW,
.STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TW,
.STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM);
csrc counters(.clk, .reset,
.StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
.InstrValidM, .LoadStallD, .CSRMWriteM,
.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM,
.InstrClassM, .DCacheMiss, .DCacheAccess,
.CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
.MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
.MTIME_CLINT, .CSRCReadValM, .IllegalCSRCAccessM);
csrm csrm(.clk, .reset, .StallW,
.CSRMWriteM, .MTrapM, .CSRAdrM,
.NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW,
.CSRWriteValM, .CSRMReadValM, .MTVEC_REGW,
.MEPC_REGW, .MCOUNTEREN_REGW, .MCOUNTINHIBIT_REGW,
.MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
.MIP_REGW, .MIE_REGW, .WriteMSTATUSM,
.IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM);
csrs csrs(.clk, .reset, .StallW,
.CSRSWriteM, .STrapM, .CSRAdrM,
.NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW,
.STATUS_TVM, .CSRWriteValM, .PrivilegeModeW,
.CSRSReadValM, .STVEC_REGW, .SEPC_REGW,
.SCOUNTEREN_REGW, .SEDELEG_REGW, .SIDELEG_REGW,
.SATP_REGW, .SIP_REGW, .SIE_REGW,
.WriteSSTATUSM, .IllegalCSRSAccessM);
csrn csrn(.clk, .reset, .StallW,
.CSRNWriteM(CSRUWriteM), .UTrapM, .CSRAdrM,
.NextEPCM, .NextCauseM, .NextMtvalM, .USTATUS_REGW,
.CSRWriteValM, .CSRNReadValM, .UEPC_REGW, .UTVEC_REGW,
.UIP_REGW, .UIE_REGW, .WriteUSTATUSM, .IllegalCSRNAccessM);
csru csru(.clk, .reset, .StallW,
.CSRUWriteM, .CSRAdrM, .CSRWriteValM, .CSRUReadValM,
.SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM,
.IllegalCSRUAccessM);
// merge CSR Reads // merge CSR Reads
assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM | CSRNReadValM; assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM | CSRNReadValM;

2
wally-pipelined/src/privileged/privileged.sv
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@ -153,7 +153,6 @@ module privileged (
/////////////////////////////////////////// ///////////////////////////////////////////
// Control and Status Registers // Control and Status Registers
/////////////////////////////////////////// ///////////////////////////////////////////
//csr csr(.*);
csr csr(.clk, .reset, csr csr(.clk, .reset,
.FlushE, .FlushM, .FlushW, .FlushE, .FlushM, .FlushW,
.StallE, .StallM, .StallW, .StallE, .StallM, .StallW,
@ -216,7 +215,6 @@ module privileged (
{IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE}, {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE},
{IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM}); {IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM});
// *** it should be possible to combine some of these faults earlier to reduce module boundary crossings and save flops dh 5 july 2021 // *** it should be possible to combine some of these faults earlier to reduce module boundary crossings and save flops dh 5 july 2021
//trap trap(.*);
trap trap(.clk, .reset, trap trap(.clk, .reset,
.InstrMisalignedFaultM, .InstrAccessFaultM, .IllegalInstrFaultM, .InstrMisalignedFaultM, .InstrAccessFaultM, .IllegalInstrFaultM,
.BreakpointFaultM, .LoadMisalignedFaultM, .StoreMisalignedFaultM, .BreakpointFaultM, .LoadMisalignedFaultM, .StoreMisalignedFaultM,