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Added note about strange vivado behavior not inferring block ram.

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Ross Thompson 2023-04-06 15:09:35 -05:00
parent d121364997
commit 270b3371f1
1 changed files with 9 additions and 9 deletions
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18
src/generic/mem/ram1p1rwe.sv
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@ -68,6 +68,8 @@ module ram1p1rwe #(parameter DEPTH=64, WIDTH=44) (
// READ first SRAM model // READ first SRAM model
// *************************************************************************** // ***************************************************************************
end else begin: ram end else begin: ram
// *** Vivado is not implementing this as block ram for some reason.
// The version with byte write enables it correctly infers block ram.
integer i; integer i;
// Read // Read
@ -82,15 +84,13 @@ module ram1p1rwe #(parameter DEPTH=64, WIDTH=44) (
// Write divided into part for bytes and part for extra msbs // Write divided into part for bytes and part for extra msbs
// Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff. // Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff.
// Therefore these always blocks use the older always @(posedge clk) // Therefore these always blocks use the older always @(posedge clk)
if(WIDTH >= 8) always @(posedge clk)
always @(posedge clk) // coverage off
// coverage off // ce only goes low when cachefsm is in READY state and Flush is asserted.
// ce only goes low when cachefsm is in READY state and Flush is asserted. // for read-only caches, we only goes high in the STATE_WRITE_LINE cachefsm state.
// for read-only caches, we only goes high in the STATE_WRITE_LINE cachefsm state. // so we can never get we=1, ce=0 for I$.
// so we can never get we=1, ce=0 for I$. if (ce & we)
if (ce & we)
// coverage on // coverage on
RAM[addr] <= #1 din; RAM[addr] <= #1 din;
end
endmodule endmodule