Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'main' of https://github.com/openhwgroup/cvw into dev

Browse Source
This commit is contained in:
David Harris 2024-09-23 11:41:25 -07:00
commit 26f51328a5
1 changed files with 1326 additions and 1337 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
testbench/testbench_fp.sv
View File

@ -35,15 +35,15 @@ module testbench_fp;
`include "parameter-defs.vh"
`ifdef VERILATOR
`ifdef VERILATOR
import "DPI-C" function string getenvval(input string env_name);
string WALLY_DIR = getenvval("WALLY");
`elsif VCS
`elsif VCS
import "DPI-C" function string getenv(input string env_name);
string WALLY_DIR = getenv("WALLY");
`else
`else
string WALLY_DIR = "$WALLY";
`endif
`endif
string FP_TESTS = {WALLY_DIR, "/tests/fp/vectors"};
string pp;
@ -82,8 +82,7 @@ module testbench_fp;
logic [P.FLEN-1:0] FpRes, FpCmpRes; // Results from each unit
logic [P.XLEN-1:0] IntRes, CmpRes; // Results from each unit
logic [P.Q_LEN-1:0] FpResExtended; // FpRes extended to same length as Ans/Res
logic [4:0] FmaFlg, CvtFlg, DivFlg; // Outputed flags
logic [4:0] CmpFlg; // Outputed flags
logic [4:0] FmaFlg, CvtFlg, DivFlg, CmpFlg; // Outputed flags
logic AnsNaN, ResNaN, NaNGood;
logic Xs, Ys, Zs; // sign of the inputs
logic [P.NE-1:0] Xe, Ye, Ze; // exponent of the inputs
@ -248,7 +247,7 @@ module testbench_fp;
end
end
end
if (TEST === "cmp" | TEST === "all") begin// if comparisons are being tested
if (TEST === "cmp" | TEST === "all") begin // if comparisons are being tested
// add the compare tests/op-ctrls/unit/fmt
Tests = {Tests, f128cmp};
OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL};
@ -796,8 +795,7 @@ module testbench_fp;
// an integer output can't be a NaN
AnsNaN = 1'b0;
ResNaN = 1'b0;
end
else if (UnitVal === `CVTFPUNIT) begin
end else if (UnitVal === `CVTFPUNIT) begin
case (OpCtrlVal[1:0])
2'b11: begin // quad
AnsNaN = &Ans[P.Q_LEN-2:P.NF]&(|Ans[P.Q_NF-1:0]);
@ -816,8 +814,7 @@ module testbench_fp;
ResNaN = &Res[P.H_LEN-2:P.H_NF]&(|Res[P.H_NF-1:0]);
end
endcase
end
else begin
end else begin
case (FmtVal)
2'b11: begin // quad
AnsNaN = &Ans[P.Q_LEN-2:P.Q_NF]&(|Ans[P.Q_NF-1:0]);
@ -890,7 +887,6 @@ module testbench_fp;
nextstate = S0;
end
endcase // case (state)
end
// Provide reset for divsqrt to reset state
@ -908,18 +904,15 @@ module testbench_fp;
// various cycle counts for different fp/int operations
// Adds vector at start of clock
always @(posedge clk) begin
// state machine element for testing
if (reset)
state <= S0;
else
state <= nextstate;
// Increment the vector when Done with each test
if (state == Done) begin
VectorNum += 1; // increment the vector
end
end
// check results on falling edge of clk
@ -975,7 +968,6 @@ module testbench_fp;
endcase
else NaNGood = 1'b0; // integers can't be NaNs
///////////////////////////////////////////////////////////////////////////////////////////////
// ||||||| ||| ||| ||||||| ||||||| ||| |||
@ -1071,7 +1063,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
output logic [P.FLEN-1:0] XPostBox,
output logic [P.NE-2:0] BiasE, // Bias of exponent
output logic [P.LOGFLEN-1:0] NfE // Number of fractional bits
);
);
localparam Q_LEN = 32'd128;
@ -1093,11 +1085,12 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
X = TestVector[8+4*(P.Q_LEN)-1:8+3*(P.Q_LEN)];
Y = TestVector[8+3*(P.Q_LEN)-1:8+2*(P.Q_LEN)];
Z = TestVector[8+2*(P.Q_LEN)-1:8+P.Q_LEN];
end
else begin
end else begin
X = TestVector[8+3*(P.Q_LEN)-1:8+2*(P.Q_LEN)];
if (OpCtrl === `MUL_OPCTRL) Y = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)]; else Y = {2'b0, {P.Q_NE-1{1'b1}}, (P.Q_NF)'(0)};
if (OpCtrl === `MUL_OPCTRL) Z = 0; else Z = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)];
if (OpCtrl === `MUL_OPCTRL) Y = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)];
else Y = {2'b0, {P.Q_NE-1{1'b1}}, (P.Q_NF)'(0)};
if (OpCtrl === `MUL_OPCTRL) Z = 0;
else Z = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)];
end
Ans = TestVector[8+(P.Q_LEN-1):8];
end
@ -1106,8 +1099,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+4*(P.D_LEN)-1:8+3*(P.D_LEN)]};
Y = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]};
Z = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+P.D_LEN]};
end
else begin
end else begin
X = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]};
if (OpCtrl === `MUL_OPCTRL) Y = {{P.Q_LEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
else Y = {{P.Q_LEN-P.D_LEN{1'b1}}, 2'b0, {P.D_NE-1{1'b1}}, (P.D_NF)'(0)};
@ -1121,8 +1113,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+4*(P.S_LEN)-1:8+3*(P.S_LEN)]};
Y = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
Z = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+P.S_LEN]};
end
else begin
end else begin
X = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
if (OpCtrl === `MUL_OPCTRL) Y = {{P.Q_LEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+(P.S_LEN)]};
else Y = {{P.Q_LEN-P.S_LEN{1'b1}}, 2'b0, {P.S_NE-1{1'b1}}, (P.S_NF)'(0)};
@ -1136,8 +1127,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+4*(P.H_LEN)-1:8+3*(P.H_LEN)]};
Y = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]};
Z = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+P.H_LEN]};
end
else begin
end else begin
X = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]};
if (OpCtrl === `MUL_OPCTRL) Y = {{P.Q_LEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
else Y = {{P.Q_LEN-P.H_LEN{1'b1}}, 2'b0, {P.H_NE-1{1'b1}}, (P.H_NF)'(0)};
@ -1415,5 +1405,4 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
.Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN,
.XSubnorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf,
.XEn, .YEn, .ZEn, .XExpMax, .XPostBox, .Bias(BiasE), .Nf(NfE));
endmodule