From 26d6f8d51afd8d094cc08a55e9946feca1261261 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 30 Dec 2021 02:25:46 +0000 Subject: [PATCH] RV32ic tests running for simple machine with no privileged unit --- addins/riscv-arch-test | 2 +- wally-pipelined/config/rv32ic/wally-config.vh | 2 +- wally-pipelined/regression/sim-wally-batch | 2 +- wally-pipelined/testbench/testbench.sv | 8 ++++++-- wally-pipelined/testbench/tests.vh | 13 +++++++++++-- 5 files changed, 20 insertions(+), 7 deletions(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index be67c99bd..307c77b26 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit be67c99bd461742aa1c100bcc0732657faae2230 +Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86 diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh index b93d77bdc..e4e0bc480 100644 --- a/wally-pipelined/config/rv32ic/wally-config.vh +++ b/wally-pipelined/config/rv32ic/wally-config.vh @@ -40,7 +40,7 @@ `define IEEE754 0 `define MISA (32'h00000104) -`define ZICSR_SUPPORTED 0 +`define ZICSR_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 0 `define COUNTERS 32 `define ZICOUNTERS_SUPPORTED 0 diff --git a/wally-pipelined/regression/sim-wally-batch b/wally-pipelined/regression/sim-wally-batch index 1dd1e68d2..a9ef8c059 100755 --- a/wally-pipelined/regression/sim-wally-batch +++ b/wally-pipelined/regression/sim-wally-batch @@ -1,3 +1,3 @@ vsim -c <