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https://github.com/openhwgroup/cvw
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Icache now works with any sized cache line a power of 2, greater than or equal to 32.
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2
wally-pipelined/src/cache/dcache.sv
vendored
2
wally-pipelined/src/cache/dcache.sv
vendored
@ -178,7 +178,7 @@ module dcache
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// variable input mux
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// variable input mux
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assign ReadDataWordM = ReadDataBlockSetsM[LsuPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]];
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assign ReadDataWordM = ReadDataBlockSetsM[LsuPAdrM[LOGWPL + LOGXLENBYTES - 1 : LOGXLENBYTES]];
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// Write Path CPU (IEU) side
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// Write Path CPU (IEU) side
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39
wally-pipelined/src/cache/icache.sv
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39
wally-pipelined/src/cache/icache.sv
vendored
@ -109,7 +109,7 @@ module icache
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logic [BLOCKLEN-1:0] ReadDataLineWayMasked [NUMWAYS-1:0];
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logic [BLOCKLEN-1:0] ReadDataLineWayMasked [NUMWAYS-1:0];
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logic [31:0] ReadLineSetsF [`ICACHE_BLOCKLENINBITS/16-1:0];
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logic [`PA_BITS-1:0] BasePAdrF, BasePAdrMaskedF;
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logic [`PA_BITS-1:0] BasePAdrF, BasePAdrMaskedF;
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logic [OFFSETLEN-1:0] BasePAdrOffsetF;
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logic [OFFSETLEN-1:0] BasePAdrOffsetF;
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@ -168,32 +168,17 @@ module icache
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// Need to OR together each way in a bitwise manner.
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// Need to OR together each way in a bitwise manner.
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// Final part of the AO Mux. First is the AND in the cacheway.
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// Final part of the AO Mux. First is the AND in the cacheway.
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or_rows #(NUMWAYS, BLOCKLEN) ReadDataAOMux(.a(ReadDataLineWayMasked), .y(ReadLineF));
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or_rows #(NUMWAYS, BLOCKLEN) ReadDataAOMux(.a(ReadDataLineWayMasked), .y(ReadLineF));
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genvar index;
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generate
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for(index = 0; index < BLOCKLEN / 16 - 1; index++) begin
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assign ReadLineSetsF[index] = ReadLineF[((index+1)*16)+16-1 : (index*16)];
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end
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assign ReadLineSetsF[BLOCKLEN/16-1] = {16'b0, ReadLineF[BLOCKLEN-1:BLOCKLEN-16]};
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endgenerate
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assign ICacheMemReadData = ReadLineSetsF[PCTagF[$clog2(BLOCKLEN / 32) + 1 : 1]];
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always_comb begin
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case (PCTagF[4:1])
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0: ICacheMemReadData = ReadLineF[31:0];
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1: ICacheMemReadData = ReadLineF[47:16];
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2: ICacheMemReadData = ReadLineF[63:32];
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3: ICacheMemReadData = ReadLineF[79:48];
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4: ICacheMemReadData = ReadLineF[95:64];
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5: ICacheMemReadData = ReadLineF[111:80];
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6: ICacheMemReadData = ReadLineF[127:96];
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7: ICacheMemReadData = ReadLineF[143:112];
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8: ICacheMemReadData = ReadLineF[159:128];
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9: ICacheMemReadData = ReadLineF[175:144];
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10: ICacheMemReadData = ReadLineF[191:160];
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11: ICacheMemReadData = ReadLineF[207:176];
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12: ICacheMemReadData = ReadLineF[223:192];
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13: ICacheMemReadData = ReadLineF[239:208];
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14: ICacheMemReadData = ReadLineF[255:224];
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15: ICacheMemReadData = {16'b0, ReadLineF[255:240]};
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endcase
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end
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// spills require storing the first cache block so it can merged
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// spills require storing the first cache block so it can merged
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// with the second
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// with the second
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// can optimize size, for now just make it the size of the data
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// can optimize size, for now just make it the size of the data
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@ -208,7 +193,7 @@ module icache
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// Detect if the instruction is compressed
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// Detect if the instruction is compressed
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assign CompressedF = FinalInstrRawF[1:0] != 2'b11;
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assign CompressedF = FinalInstrRawF[1:0] != 2'b11;
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assign spill = PCF[4:1] == 4'b1111 ? 1'b1 : 1'b0;
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assign spill = &PCF[$clog2(BLOCKLEN/32)+1:1];
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// to compute the fetch address we need to add the bit shifted
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// to compute the fetch address we need to add the bit shifted
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