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Fixed comment typo
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@ -63,7 +63,7 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) (
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// Otherwise, the divisor is retained and the residual and result
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// Otherwise, the divisor is retained and the residual and result
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// are fed back for the next iteration.
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// are fed back for the next iteration.
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// Residual WS/SC registers/initializaiton mux
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// Residual WS/SC registers/initialization mux
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mux2 #(P.DIVb+4) wsmux(WS[P.DIVCOPIES], X, IFDivStartE, WSN);
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mux2 #(P.DIVb+4) wsmux(WS[P.DIVCOPIES], X, IFDivStartE, WSN);
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mux2 #(P.DIVb+4) wcmux(WC[P.DIVCOPIES], '0, IFDivStartE, WCN);
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mux2 #(P.DIVb+4) wcmux(WC[P.DIVCOPIES], '0, IFDivStartE, WCN);
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flopen #(P.DIVb+4) wsreg(clk, FDivBusyE, WSN, WS[0]);
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flopen #(P.DIVb+4) wsreg(clk, FDivBusyE, WSN, WS[0]);
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