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Fixed comment typo

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David Harris 2023-07-04 11:34:58 -07:00
parent b04763bcf2
commit 269bb688ea
1 changed files with 1 additions and 1 deletions
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src/fpu/fdivsqrt/fdivsqrtiter.sv
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@ -63,7 +63,7 @@ module fdivsqrtiter import cvw::*; #(parameter cvw_t P) (
// Otherwise, the divisor is retained and the residual and result // Otherwise, the divisor is retained and the residual and result
// are fed back for the next iteration. // are fed back for the next iteration.
// Residual WS/SC registers/initializaiton mux // Residual WS/SC registers/initialization mux
mux2 #(P.DIVb+4) wsmux(WS[P.DIVCOPIES], X, IFDivStartE, WSN); mux2 #(P.DIVb+4) wsmux(WS[P.DIVCOPIES], X, IFDivStartE, WSN);
mux2 #(P.DIVb+4) wcmux(WC[P.DIVCOPIES], '0, IFDivStartE, WCN); mux2 #(P.DIVb+4) wcmux(WC[P.DIVCOPIES], '0, IFDivStartE, WCN);
flopen #(P.DIVb+4) wsreg(clk, FDivBusyE, WSN, WS[0]); flopen #(P.DIVb+4) wsreg(clk, FDivBusyE, WSN, WS[0]);