Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

Browse Source
This commit is contained in:
David Harris 2021-10-10 12:26:15 -07:00
commit 266c706804
2 changed files with 8 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
wally-pipelined/src/fpu/fpu.sv
View File

@ -204,15 +204,15 @@ module fpu (
// - if not captured any forwarded inputs will change durring computation // - if not captured any forwarded inputs will change durring computation
// - this problem is caused by stalling the execute stage // - this problem is caused by stalling the execute stage
// - the other units don't have this problem, only div/sqrt stalls the execute stage // - the other units don't have this problem, only div/sqrt stalls the execute stage
flopenrc #(64) reg_input1 (.d({XSgnE, XExpE, XManE[51:0]}), .q(DivInput1E), floprc #(64) reg_input1 (.d({XSgnE, XExpE, XManE[51:0]}), .q(DivInput1E),
.en(1'b1), .clear(FDivSqrtDoneE), .clear(FDivSqrtDoneE),
.reset(reset), .clk(FDivBusyE)); .reset(reset), .clk(FDivBusyE));
flopenrc #(64) reg_input2 (.d({YSgnE, YExpE, YManE[51:0]}), .q(DivInput2E), floprc #(64) reg_input2 (.d({YSgnE, YExpE, YManE[51:0]}), .q(DivInput2E),
.en(1'b1), .clear(FDivSqrtDoneE), .clear(FDivSqrtDoneE),
.reset(reset), .clk(FDivBusyE)); .reset(reset), .clk(FDivBusyE));
flopenrc #(6) reg_input3 (.d({XNaNE, YNaNE, XInfE, YInfE, XZeroE, YZeroE}), floprc #(6) reg_input3 (.d({XNaNE, YNaNE, XInfE, YInfE, XZeroE, YZeroE}),
.q({XNaNQ, YNaNQ, XInfQ, YInfQ, XZeroQ, YZeroQ}), .q({XNaNQ, YNaNQ, XInfQ, YInfQ, XZeroQ, YZeroQ}),
.en(1'b1), .clear(FDivSqrtDoneE), .clear(FDivSqrtDoneE),
.reset(reset), .clk(FDivBusyE)); .reset(reset), .clk(FDivBusyE));
// fpdivsqrt using Goldschmidt's iteration // fpdivsqrt using Goldschmidt's iteration

6
wally-pipelined/src/ifu/bpred.sv
View File

@ -192,17 +192,15 @@ module bpred
// The prediction and its results need to be passed through the pipeline // The prediction and its results need to be passed through the pipeline
// *** for other predictors will will be different. // *** for other predictors will will be different.
flopenrc #(2) BPPredRegD(.clk(clk), flopenr #(2) BPPredRegD(.clk(clk),
.reset(reset), .reset(reset),
.en(~StallD), .en(~StallD),
.clear(1'b0),
.d(BPPredF), .d(BPPredF),
.q(BPPredD)); .q(BPPredD));
flopenrc #(2) BPPredRegE(.clk(clk), flopenr #(2) BPPredRegE(.clk(clk),
.reset(reset), .reset(reset),
.en(~StallE), .en(~StallE),
.clear(1'b0),
.d(BPPredD), .d(BPPredD),
.q(BPPredE)); .q(BPPredE));