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testbench update b/c QEMU extends 32b CSRs to 64b

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bbracker 2021-06-20 09:24:19 -04:00
parent 7aa2f0d953
commit 2611d214a6
1 changed files with 3 additions and 3 deletions
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6
wally-pipelined/testbench/testbench-linux.sv
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@ -407,12 +407,12 @@ module testbench();
end \
if (``CSR``name == MSTATUSstring) begin \
if (``PATH``.``CSR``_REGW != ((``expected``CSR) | 64'ha00000000)) begin \
$display("%0t ps, instr %0d: %s does not equal %s Expected: %x, %x", $time, instrs, ``CSR``name, expected``CSR``name, ``PATH``.``CSR``_REGW, (``expected``CSR) | 64'ha00000000); \
$display("%0t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, ``CSR``name, expected``CSR``name, ``PATH``.``CSR``_REGW, (``expected``CSR) | 64'ha00000000); \
`ERROR \
end \
end else \
if (``PATH``.``CSR``_REGW != ``expected``CSR) begin \
$display("%0t ps, instr %0d: %s does not Equal %s expected: %x, %x", $time, instrs, ``CSR``name, expected``CSR``name, ``PATH``.``CSR``_REGW, ``expected``CSR); \
if (``PATH``.``CSR``_REGW != ``expected``CSR[$bits(``PATH``.``CSR``_REGW)-1:0]) begin \
$display("%0t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, ``CSR``name, expected``CSR``name, ``PATH``.``CSR``_REGW, ``expected``CSR); \
`ERROR \
end \
end else begin \