diff --git a/config/rv32gc/wally-config.vh b/config/rv32gc/wally-config.vh index 2e06c03d4..d9d770f82 100644 --- a/config/rv32gc/wally-config.vh +++ b/config/rv32gc/wally-config.vh @@ -43,7 +43,7 @@ `define COUNTERS 32 `define ZICOUNTERS_SUPPORTED 1 `define ZFH_SUPPORTED 0 -`define SSTC_SUPPORTED 0 +`define SSTC_SUPPORTED 1 // LSU microarchitectural Features `define BUS_SUPPORTED 1 diff --git a/config/rv64gc/wally-config.vh b/config/rv64gc/wally-config.vh index fe6ecdc67..4ef3bf517 100644 --- a/config/rv64gc/wally-config.vh +++ b/config/rv64gc/wally-config.vh @@ -44,7 +44,7 @@ `define COUNTERS 32 `define ZICOUNTERS_SUPPORTED 1 `define ZFH_SUPPORTED 0 -`define SSTC_SUPPORTED 0 +`define SSTC_SUPPORTED 1 // LSU microarchitectural Features `define BUS_SUPPORTED 1 diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index 253d02457..e47a44426 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -102,10 +102,10 @@ module csrs #(parameter flopens #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW); if (`SSTC_SUPPORTED) begin if (`XLEN == 64) - flopenr #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, STIMECMP_REGW); + flopenl #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 64'hFFFFFFFFFFFFFFFF, STIMECMP_REGW); else begin - flopenr #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, STIMECMP_REGW[31:0]); - flopenr #(`XLEN) STIMECMPHreg(clk, reset, WriteSTIMECMPHM, CSRWriteValM, STIMECMP_REGW[63:32]); + flopenl #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[31:0]); + flopenl #(`XLEN) STIMECMPHreg(clk, reset, WriteSTIMECMPHM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[63:32]); end end else assign STIMECMP_REGW = 0; diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index 1171786f4..f3f963d8b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -125,20 +125,31 @@ cause_m_time_interrupt: lw t2, 0(t5) // low word of MTIME lw t6, 4(t5) // high word of MTIME add t3, t2, t3 // add desired offset to the current time - bgtu t3, t2, nowrap // check new time exceeds current time (no wraparound) + bgtu t3, t2, nowrap_m // check new time exceeds current time (no wraparound) addi t6, t6, 1 // if wrap, increment most significant word sw t6,4(t4) // store into most significant word of MTIMECMP -nowrap: +nowrap_m: sw t3, 0(t4) // store into least significant word of MTIMECMP -time_loop: +time_loop_m: addi a3, a3, -1 - bnez a3, time_loop // go through this loop for [a3 value] iterations before returning without performing interrupt + bnez a3, time_loop_m // go through this loop for [a3 value] iterations before returning without performing interrupt ret cause_s_time_interrupt: - li t3, 0x20 - csrs mip, t3 // set supervisor time interrupt pending. SIP is a subset of MIP, so writing this should also change MIP. - nop // added extra nops in so the csrs can get through the pipeline before returning. + li t3, 0x30 // Desired offset from the present time + mv a3, t3 // copy value in to know to stop waiting for interrupt after this many cycles + la t5, 0x0200BFF8 // MTIME register in CLINT *** we still read from mtime since stimecmp is compared to it + lw t2, 0(t5) // low word of MTIME + lw t6, 4(t5) // high word of MTIME + add t3, t2, t3 // add desired offset to the current time + bgtu t3, t2, nowrap_s // check new time exceeds current time (no wraparound) + addi t6, t6, 1 // if wrap, increment most significant word +nowrap_s: + csrw stimecmp, t3 // store into STIMECMP + csrw stimecmph, t6 // store into STIMECMPH +time_loop_s: + addi a3, a3, -1 + bnez a3, time_loop_s // go through this loop for [a3 value] iterations before returning without performing interrupt ret cause_m_soft_interrupt: @@ -545,8 +556,12 @@ soft_interrupt_\MODE\(): time_interrupt_\MODE\(): la t0, 0x02004000 // MTIMECMP register in CLINT li t2, 0xFFFFFFFF - sw t2, 0(t0) // reset interrupt by setting mtimecmp to 0xFFFFFFFF - + sw t2, 0(t0) // reset interrupt by setting mtimecmp to max + //sw t2, 4(t0) // reset interrupt by setting mtimecmpH to max + csrw stimecmp, t2 // reset stime interrupts by doing the same to stimecmp and stimecmpH. + csrw stimecmph, t2 + + li t0, 0x20 csrc \MODE\()ip, t0 lw ra, -4(sp) // load return address from stack into ra (the address to return to after the loop is complete) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index 576636deb..00e235f35 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -127,22 +127,30 @@ cause_m_time_interrupt: lw t2, 0(t5) // low word of MTIME lw t6, 4(t5) // high word of MTIME add t3, t2, t3 // add desired offset to the current time - bgtu t3, t2, nowrap // check new time exceeds current time (no wraparound) + bgtu t3, t2, nowrap_m // check new time exceeds current time (no wraparound) addi t6, t6, 1 // if wrap, increment most significant word sw t6,4(t4) // store into most significant word of MTIMECMP -nowrap: +nowrap_m: sw t3, 0(t4) // store into least significant word of MTIMECMP -time_loop: +time_loop_m: addi a3, a3, -1 - bnez a3, time_loop // go through this loop for [a3 value] iterations before returning without performing interrupt + bnez a3, time_loop_m // go through this loop for [a3 value] iterations before returning without performing interrupt ret cause_s_time_interrupt: - li t3, 0x20 - csrs mip, t3 // set supervisor time interrupt pending. - nop // added extra nops in so the csrs can get through the pipeline before returning. + li t3, 0x30 // Desired offset from the present time + mv a3, t3 // copy value in to know to stop waiting for interrupt after this many cycles + // la t4, 0x02004000 // MTIMECMP register in CLINT + la t5, 0x0200BFF8 // MTIME register in CLINT *** we still read from mtime since stimecmp is compared to it + lw t2, 0(t5) // low word of MTIME + lw t6, 4(t5) // high word of MTIME + add t3, t2, t3 // add desired offset to the current time + csrw stimecmp, t3 // store into most significant word of STIMECMP +time_loop_s: + addi a3, a3, -1 + bnez a3, time_loop_s // go through this loop for [a3 value] iterations before returning without performing interrupt ret - + cause_m_soft_interrupt: la t3, 0x02000000 // MSIP register in CLINT li t4, 1 // 1 in the lsb @@ -539,7 +547,8 @@ soft_interrupt_\MODE\(): time_interrupt_\MODE\(): la t0, 0x02004000 // MTIMECMP register in CLINT li t2, 0xFFFFFFFF - sd t2, 0(t0) // reset interrupt by setting mtimecmp to 0xFFFFFFFF + sd t2, 0(t0) // reset interrupt by setting mtimecmp to max + csrw stimecmp, t2 // reset stime interrupts by doing the same. li t0, 0x20 csrc \MODE\()ip, t0