Fixed sumtest reference output; added embench benchmark directory

addins/embench-iot

@@ -1 +1 @@
-Subproject commit 261a65e0a2d3e8d62d81b1d8fe7e309a096bc6a9
+Subproject commit 4530b3aef3b25f5001dddb884b77f8ccfba1dca6

benchmarks/embench/Makefile

@@ -0,0 +1,15 @@
+# Makefile added 1/20/22 David_Harris@hmc.edu
+# Compile Embench for Wally
+
+all: Makefile
+	../../addins/embench-iot/build_all.py --arch riscv32 --chip generic --board ri5cyverilator --cflags "-O2 -march=rv32i -mabi=ilp32 -mcmodel=medany" --cc riscv64-unknown-elf-gcc 
+	./benchmark_size.py 
+	./benchmark_speed.py
+
+# view with
+# more `ls -t | head -1`
+
+# --cflags "-O2 -g -nostartfiles"
+
+
+#riscv64-unknown-elf-gcc -O2 -g -nostartfiles -I/home/harris/riscv-wally/addins/embench-iot/support -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/boards/ri5cyverilator -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/chips/generic -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32 -DCPU_MHZ=1 -DWARMUP_HEAT=1 -o main.o /home/harris/riscv-wally/addins/embench-iot/support/main.c

benchmarks/embench/Makefile~

@@ -0,0 +1,7 @@
+# Makefile added 1/20/22 David_Harris@hmc.edu
+# Compile Embench for Wally
+
+all: Makefile
+	./build_all.py --arch riscv32 --chip generic --board ri5cyverilator --cc riscv64-unknown-elf-gcc 
+	./benchmark_size.py 
+	./benchmark_speed.py

examples/asm/sumtest/sumtest.reference_output

@@ -1,2 +1,2 @@
 000000000000000A
-000000000000001C
+000000000000001D

setup.sh

@@ -4,7 +4,7 @@
 # David_Harris@hmc.edu and kekim@hmc.edu 1 December 2021
 # Set up tools for riscv-wally
 
-echo "Executing wally-setup.sh"
+echo "Executing Wally setup.sh"
 
 # Path to RISC-V Tools
 export RISCV=/opt/riscv   # change this if you installed the tools in a different location