From 169539f7731770818f0b4189d2c098a0cf94c569 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 31 May 2023 10:02:34 -0500 Subject: [PATCH 1/7] Cleanup parameterization for verilator 5.010. --- src/uncore/ram_ahb.sv | 3 ++- src/uncore/rom_ahb.sv | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv index 1391a5691..b7ec13457 100644 --- a/src/uncore/ram_ahb.sv +++ b/src/uncore/ram_ahb.sv @@ -28,7 +28,8 @@ `define RAM_LATENCY 0 -module ram_ahb import cvw::*; #(parameter cvw_t P, BASE=0, RANGE = 65535) ( +module ram_ahb import cvw::*; #(parameter cvw_t P, + parameter BASE=0, RANGE = 65535) ( input logic HCLK, HRESETn, input logic HSELRam, input logic [P.PA_BITS-1:0] HADDR, diff --git a/src/uncore/rom_ahb.sv b/src/uncore/rom_ahb.sv index 79a5405e1..abb75277f 100644 --- a/src/uncore/rom_ahb.sv +++ b/src/uncore/rom_ahb.sv @@ -26,7 +26,8 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module rom_ahb import cvw::*; #(parameter cvw_t P, BASE=0, RANGE = 65535) ( +module rom_ahb import cvw::*; #(parameter cvw_t P, + parameter BASE=0, RANGE = 65535) ( input logic HCLK, HRESETn, input logic HSELRom, input logic [P.PA_BITS-1:0] HADDR, From a963f0af3af727683ccb6f000e01f584164f1790 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 31 May 2023 10:44:23 -0500 Subject: [PATCH 2/7] Updated source code to be compatible with verilator 5.011 for lint only. --- config/shared/BranchPredictorType.vh | 2 +- config/shared/parameter-defs.vh | 4 ++++ src/ifu/bpred/RASPredictor.sv | 3 ++- src/ifu/bpred/btb.sv | 3 ++- src/ifu/bpred/icpred.sv | 3 ++- src/mmu/tlb/tlbcam.sv | 3 ++- src/mmu/tlb/tlbcamline.sv | 3 ++- src/mmu/tlb/tlbram.sv | 3 ++- src/privileged/csr.sv | 5 ++++- src/uncore/ahbapbbridge.sv | 3 ++- src/wally/wallypipelinedsoc.sv | 1 - 11 files changed, 23 insertions(+), 10 deletions(-) diff --git a/config/shared/BranchPredictorType.vh b/config/shared/BranchPredictorType.vh index 0f62fb954..e252de249 100644 --- a/config/shared/BranchPredictorType.vh +++ b/config/shared/BranchPredictorType.vh @@ -1,3 +1,3 @@ -typedef enum {BP_TWOBIT, BP_GSHARE, BP_GLOBAL, BP_GSHARE_BASIC, +typedef enum logic[3:0] {BP_TWOBIT, BP_GSHARE, BP_GLOBAL, BP_GSHARE_BASIC, BP_GLOBAL_BASIC, BP_LOCAL_BASIC, BP_LOCAL_AHEAD, BP_LOCAL_REPAIR} BranchPredictorType; diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index 1dd28b746..271fc7fe8 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -72,7 +72,11 @@ parameter cvw_t P = '{ PLIC_GPIO_ID : PLIC_GPIO_ID, PLIC_UART_ID : PLIC_UART_ID, BPRED_SUPPORTED : BPRED_SUPPORTED, + /* verilator lint_off ENUMVALUE */ + // *** definitely need to fix this. + // it thinks we are casting from the enum type to BPRED_TYPE. BPRED_TYPE : BPRED_TYPE, + /* verilator lint_off ENUMVALUE */ BPRED_SIZE : BPRED_SIZE, BPRED_NUM_LHR : BPRED_NUM_LHR, BTB_SIZE : BTB_SIZE, diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv index 85b300fd0..5dd3cf7b2 100644 --- a/src/ifu/bpred/RASPredictor.sv +++ b/src/ifu/bpred/RASPredictor.sv @@ -27,7 +27,8 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module RASPredictor import cvw::*; #(parameter cvw_t P, StackSize = 16 )( +module RASPredictor import cvw::*; #(parameter cvw_t P, + parameter StackSize = 16 )( input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM, diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index 296ffb716..5279f867a 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -28,7 +28,8 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module btb import cvw::*; #(parameter cvw_t P, Depth = 10 ) ( +module btb import cvw::*; #(parameter cvw_t P, + parameter Depth = 10 ) ( input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, FlushD, FlushE, FlushM, FlushW, diff --git a/src/ifu/bpred/icpred.sv b/src/ifu/bpred/icpred.sv index 64324e26e..65e60c59c 100644 --- a/src/ifu/bpred/icpred.sv +++ b/src/ifu/bpred/icpred.sv @@ -26,7 +26,8 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module icpred import cvw::*; #(parameter cvw_t P, INSTR_CLASS_PRED = 1)( +module icpred import cvw::*; #(parameter cvw_t P, + parameter INSTR_CLASS_PRED = 1)( input logic clk, reset, input logic StallF, StallD, StallE, StallM, StallW, input logic FlushD, FlushE, FlushM, FlushW, diff --git a/src/mmu/tlb/tlbcam.sv b/src/mmu/tlb/tlbcam.sv index 38bc8c4c9..7a4100829 100644 --- a/src/mmu/tlb/tlbcam.sv +++ b/src/mmu/tlb/tlbcam.sv @@ -29,7 +29,8 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module tlbcam import cvw::*; #(parameter cvw_t P, TLB_ENTRIES = 8, KEY_BITS = 20, SEGMENT_BITS = 10) ( +module tlbcam import cvw::*; #(parameter cvw_t P, + parameter TLB_ENTRIES = 8, KEY_BITS = 20, SEGMENT_BITS = 10) ( input logic clk, reset, input logic [P.VPN_BITS-1:0] VPN, input logic [1:0] PageTypeWriteVal, diff --git a/src/mmu/tlb/tlbcamline.sv b/src/mmu/tlb/tlbcamline.sv index 127326c20..55023006f 100644 --- a/src/mmu/tlb/tlbcamline.sv +++ b/src/mmu/tlb/tlbcamline.sv @@ -29,7 +29,8 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module tlbcamline import cvw::*; #(parameter cvw_t P, KEY_BITS = 20, SEGMENT_BITS = 10) ( +module tlbcamline import cvw::*; #(parameter cvw_t P, + parameter KEY_BITS = 20, SEGMENT_BITS = 10) ( input logic clk, reset, input logic [P.VPN_BITS-1:0] VPN, // The requested page number to compare against the key input logic [P.ASID_BITS-1:0] SATP_ASID, diff --git a/src/mmu/tlb/tlbram.sv b/src/mmu/tlb/tlbram.sv index 693d841a6..eb8dedca7 100644 --- a/src/mmu/tlb/tlbram.sv +++ b/src/mmu/tlb/tlbram.sv @@ -29,7 +29,8 @@ //////////////////////////////////////////////////////////////////////////////////////////////// -module tlbram import cvw::*; #(parameter cvw_t P, TLB_ENTRIES = 8) ( +module tlbram import cvw::*; #(parameter cvw_t P, + parameter TLB_ENTRIES = 8) ( input logic clk, reset, input logic [P.XLEN-1:0] PTE, input logic [TLB_ENTRIES-1:0] Matches, WriteEnables, diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index 6affbb5d3..4eacc4d0a 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -28,7 +28,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module csr import cvw::*; #(parameter cvw_t P, MIP = 12'h344, SIP = 12'h144) ( +module csr import cvw::*; #(parameter cvw_t P) ( input logic clk, reset, input logic FlushM, FlushW, input logic StallE, StallM, StallW, @@ -91,6 +91,9 @@ module csr import cvw::*; #(parameter cvw_t P, MIP = 12'h344, SIP = 12'h144) ( output logic BigEndianM // memory access is big-endian based on privilege mode and STATUS register endian fields ); + localparam MIP = 12'h344; + localparam SIP = 12'h144; + logic [P.XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRCReadValM; logic [P.XLEN-1:0] CSRReadValM; logic [P.XLEN-1:0] CSRSrcM; diff --git a/src/uncore/ahbapbbridge.sv b/src/uncore/ahbapbbridge.sv index bfbe9caaf..5aed30300 100644 --- a/src/uncore/ahbapbbridge.sv +++ b/src/uncore/ahbapbbridge.sv @@ -25,7 +25,8 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module ahbapbbridge import cvw::*; #(parameter cvw_t P, PERIPHS = 2) ( +module ahbapbbridge import cvw::*; #(parameter cvw_t P, + parameter PERIPHS = 2) ( input logic HCLK, HRESETn, input logic [PERIPHS-1:0] HSEL, input logic [P.PA_BITS-1:0] HADDR, diff --git a/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv index 519c715e8..03974fe51 100644 --- a/src/wally/wallypipelinedsoc.sv +++ b/src/wally/wallypipelinedsoc.sv @@ -28,7 +28,6 @@ `include "config.vh" //import cvw::*; // global CORE-V-Wally parameters -`include "wally-config.vh" module wallypipelinedsoc import cvw::*; ( input logic clk, From 76fd76c1557182fcae4ca8e7cd57a904ccdc4caa Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 31 May 2023 11:00:38 -0500 Subject: [PATCH 3/7] Oups forgot to include updates to the lint script itself. --- sim/lint-wally | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/lint-wally b/sim/lint-wally index 8de8010df..acad750b6 100755 --- a/sim/lint-wally +++ b/sim/lint-wally @@ -8,7 +8,7 @@ basepath=$(dirname $0)/.. for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do #for config in rv64gc; do echo "$config linting..." - if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/wally/cvw.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then + if !($verilator --no-timing --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/wally/cvw.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then echo "Exiting after $config lint due to errors or warnings" exit 1 fi From 3bd5bbce487f09e5fc493379db670993f2678546 Mon Sep 17 00:00:00 2001 From: James Stine Date: Mon, 5 Jun 2023 11:03:06 -0500 Subject: [PATCH 4/7] Update some spacing to make it look better --- src/fpu/fcvt.sv | 55 +++++++++++++++++++++---------------------------- 1 file changed, 24 insertions(+), 31 deletions(-) diff --git a/src/fpu/fcvt.sv b/src/fpu/fcvt.sv index 640e4e82d..1ae2f6721 100644 --- a/src/fpu/fcvt.sv +++ b/src/fpu/fcvt.sv @@ -28,20 +28,20 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module fcvt import cvw::*; #(parameter cvw_t P) ( - input logic Xs, // input's sign - input logic [P.NE-1:0] Xe, // input's exponent - input logic [P.NF:0] Xm, // input's fraction - input logic [P.XLEN-1:0] Int, // integer input - from IEU - input logic [2:0] OpCtrl, // choose which opperation (look below for values) - input logic ToInt, // is fp->int (since it's writting to the integer register) - input logic XZero, // is the input zero - input logic [P.FMTBITS-1:0] Fmt, // the input's precision (11=quad 01=double 00=single 10=half) - output logic [P.NE:0] Ce, // the calculated expoent - output logic [P.LOGCVTLEN-1:0] ShiftAmt, // how much to shift by - output logic ResSubnormUf,// does the result underflow or is subnormal - output logic Cs, // the result's sign - output logic IntZero, // is the integer zero? - output logic [P.CVTLEN-1:0] LzcIn // input to the Leading Zero Counter (priority encoder) + input logic Xs, // input's sign + input logic [P.NE-1:0] Xe, // input's exponent + input logic [P.NF:0] Xm, // input's fraction + input logic [P.XLEN-1:0] Int, // integer input - from IEU + input logic [2:0] OpCtrl, // choose which opperation (look below for values) + input logic ToInt, // is fp->int (since it's writting to the integer register) + input logic XZero, // is the input zero + input logic [P.FMTBITS-1:0] Fmt, // the input's precision (11=quad 01=double 00=single 10=half) + output logic [P.NE:0] Ce, // the calculated expoent + output logic [P.LOGCVTLEN-1:0] ShiftAmt, // how much to shift by + output logic ResSubnormUf, // does the result underflow or is subnormal + output logic Cs, // the result's sign + output logic IntZero, // is the integer zero? + output logic [P.CVTLEN-1:0] LzcIn // input to the Leading Zero Counter (priority encoder) ); // OpCtrls: @@ -54,17 +54,16 @@ module fcvt import cvw::*; #(parameter cvw_t P) ( // bit 2 bit 1 bit 0 // for example: signed long -> single floating point has the OpCode 101 - logic [P.FMTBITS-1:0] OutFmt; // format of the output - logic [P.XLEN-1:0] PosInt; // the positive integer input - logic [P.XLEN-1:0] TrimInt; // integer trimmed to the correct size - logic [P.NE-2:0] NewBias; // the bias of the final result - logic [P.NE-1:0] OldExp; // the old exponent - logic Signed; // is the opperation with a signed integer? - logic Int64; // is the integer 64 bits? - logic IntToFp; // is the opperation an int->fp conversion? - logic [P.CVTLEN:0] LzcInFull; // input to the Leading Zero Counter (priority encoder) - logic [P.LOGCVTLEN-1:0] LeadingZeros; // output from the LZC - + logic [P.FMTBITS-1:0] OutFmt; // format of the output + logic [P.XLEN-1:0] PosInt; // the positive integer input + logic [P.XLEN-1:0] TrimInt; // integer trimmed to the correct size + logic [P.NE-2:0] NewBias; // the bias of the final result + logic [P.NE-1:0] OldExp; // the old exponent + logic Signed; // is the opperation with a signed integer? + logic Int64; // is the integer 64 bits? + logic IntToFp; // is the opperation an int->fp conversion? + logic [P.CVTLEN:0] LzcInFull; // input to the Leading Zero Counter (priority encoder) + logic [P.LOGCVTLEN-1:0] LeadingZeros; // output from the LZC // seperate OpCtrl for code readability assign Signed = OpCtrl[0]; @@ -79,7 +78,6 @@ module fcvt import cvw::*; #(parameter cvw_t P) ( else if (P.FPSIZES == 3 | P.FPSIZES == 4) assign OutFmt = IntToFp ? Fmt : OpCtrl[1:0]; - /////////////////////////////////////////////////////////////////////////// // negation /////////////////////////////////////////////////////////////////////////// @@ -143,7 +141,6 @@ module fcvt import cvw::*; #(parameter cvw_t P) ( assign NewBias = ToInt ? (P.NE-1)'(1) : NewBiasToFp; end - // select the old exponent // int -> fp : largest bias + XLEN-1 // fp -> ??? : XExp @@ -185,13 +182,11 @@ module fcvt import cvw::*; #(parameter cvw_t P) ( // oldexp - biasold - LeadingZeros + newbias assign Ce = {1'b0, OldExp} - (P.NE+1)'(P.BIAS) - {{P.NE-P.LOGCVTLEN+1{1'b0}}, (LeadingZeros)} + {2'b0, NewBias}; - // find if the result is dnormal or underflows // - if Calculated expoenent is 0 or negitive (and the input/result is not exactaly 0) // - can't underflow an integer to Fp conversion assign ResSubnormUf = (~|Ce | Ce[P.NE])&~XZero&~IntToFp; - /////////////////////////////////////////////////////////////////////////// // shifter /////////////////////////////////////////////////////////////////////////// @@ -212,7 +207,6 @@ module fcvt import cvw::*; #(parameter cvw_t P) ( if(ToInt) ShiftAmt = Ce[P.LOGCVTLEN-1:0]&{P.LOGCVTLEN{~Ce[P.NE]}}; else if (ResSubnormUf) ShiftAmt = (P.LOGCVTLEN)'(P.NF-1)+Ce[P.LOGCVTLEN-1:0]; else ShiftAmt = LeadingZeros; - /////////////////////////////////////////////////////////////////////////// // sign @@ -230,4 +224,3 @@ module fcvt import cvw::*; #(parameter cvw_t P) ( else Cs = Xs; endmodule - From ac3253203dffbb9ea0be570911d2245bb8be55e0 Mon Sep 17 00:00:00 2001 From: James Stine Date: Mon, 5 Jun 2023 11:03:59 -0500 Subject: [PATCH 5/7] Update fcvt tests for l.s/lu.s and s.l/s.lu that were missing --- tests/coverage/fpu.S | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S index 879980899..7e67b8ab5 100644 --- a/tests/coverage/fpu.S +++ b/tests/coverage/fpu.S @@ -94,7 +94,10 @@ main: fcvt.wu.q a0, ft3 fcvt.l.q a0, ft3 fcvt.lu.q a0, ft3 - + fcvt.l.s a0, ft0 + fcvt.lu.s a0, ft0 + fcvt.s.l ft0, t0 + fcvt.s.lu ft0, t0 // Tests verfying that half and quad floating point convertion instructions are not supported by rv64gc # fcvt.h.d ft3, ft0 // Somehow this instruction is taking the route on line 124 From 4425946db8f61bba0a826bb9a2801da39edf0503 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 5 Jun 2023 11:49:16 -0500 Subject: [PATCH 6/7] Fixed typo in coremark makefile. --- benchmarks/coremark/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile index 7b30dcd3e..2c5bf957b 100644 --- a/benchmarks/coremark/Makefile +++ b/benchmarks/coremark/Makefile @@ -4,7 +4,7 @@ PORT_DIR = $(CURDIR)/riscv64-baremetal cmbase=../../addins/coremark -work_dir= ../benchmarks/coremark/work +work_dir= work XLEN ?=64 sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h \ $(cmbase)/core_matrix.c $(cmbase)/core_state.c $(cmbase)/core_util.c \ From 918464c236e9bb168a2c7ecdbf0606c6ce89b9c9 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 5 Jun 2023 15:42:05 -0500 Subject: [PATCH 7/7] Found the coremark performance issue. The testbench was continuously forcing the BTB to all zeros. Once fixed it resolved the performance problem. --- src/privileged/csrc.sv | 2 +- testbench/testbench.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv index e7e50a7d3..e1104f699 100644 --- a/src/privileged/csrc.sv +++ b/src/privileged/csrc.sv @@ -98,7 +98,7 @@ module csrc import cvw::*; #(parameter cvw_t P) ( assign CounterEvent[3] = InstrClassM[0] & InstrValidNotFlushedM; // branch instruction assign CounterEvent[4] = InstrClassM[1] & ~InstrClassM[2] & InstrValidNotFlushedM; // jump and not return instructions assign CounterEvent[5] = InstrClassM[2] & InstrValidNotFlushedM; // return instructions - assign CounterEvent[6] = BPWrongM & InstrValidNotFlushedM; // branch predictor wrong + assign CounterEvent[6] = BPWrongM & InstrValidNotFlushedM; // branch predictor wrong assign CounterEvent[7] = BPDirPredWrongM & InstrValidNotFlushedM; // Branch predictor wrong direction assign CounterEvent[8] = BTAWrongM & InstrValidNotFlushedM; // branch predictor wrong target assign CounterEvent[9] = RASPredPCWrongM & InstrValidNotFlushedM; // return address stack wrong address diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 6184cefb0..bffd80b96 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -554,7 +554,7 @@ module testbench; always @(*) begin if(reset) begin for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin - force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; + dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; end for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;