From 25d9d5299495ded8f68523b339cd753ab61b789c Mon Sep 17 00:00:00 2001
From: Kevin Kim <kevindkim723@gmail.com>
Date: Sun, 5 Feb 2023 01:04:39 +0000
Subject: [PATCH] modularized byte instruction handling into byte.sv; passes
 lint

---
 pipelined/src/ieu/byte.sv | 44 +++++++++++++++++++++++++++++++++++++++
 pipelined/src/ieu/zbb.sv  | 11 +++-------
 2 files changed, 47 insertions(+), 8 deletions(-)
 create mode 100644 pipelined/src/ieu/byte.sv

diff --git a/pipelined/src/ieu/byte.sv b/pipelined/src/ieu/byte.sv
new file mode 100644
index 000000000..17ab652f2
--- /dev/null
+++ b/pipelined/src/ieu/byte.sv
@@ -0,0 +1,44 @@
+///////////////////////////////////////////
+// clmul.sv
+//
+// Written: Kevin Kim <kekim@hmc.edu>
+// Created: 1 February 2023
+// Modified: 
+//
+// Purpose: Carry-Less multiplication top-level unit
+//
+// Documentation: RISC-V System on Chip Design Chapter ***
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module byteUnit #(parameter WIDTH=32) (
+  input  logic [WIDTH-1:0] A,             // Operands
+  output logic [WIDTH-1:0] OrcBResult,    // OrcB result
+  output logic [WIDTH-1:0] Rev8Result);   // Rev8 result
+
+  genvar i;
+
+  for (i=0;i<WIDTH;i+=8) begin:loop
+    assign OrcBResult[i+7:i] = {8{|A[i+7:i]}};
+    assign Rev8Result[WIDTH-i:WIDTH-i-7] = A[i+7:i];
+  end
+
+endmodule
\ No newline at end of file
diff --git a/pipelined/src/ieu/zbb.sv b/pipelined/src/ieu/zbb.sv
index e3803e176..860fd2c42 100644
--- a/pipelined/src/ieu/zbb.sv
+++ b/pipelined/src/ieu/zbb.sv
@@ -44,18 +44,13 @@ module zbb #(parameter WIDTH=32) (
   logic [WIDTH-1:0] ctzResult;         // trailing zeros result
   logic [WIDTH-1:0] cpopResult;        // population count result
 
-  cnt cnt(.A(A), .W64(W64), .clzResult(clzResult), .ctzResult(ctzResult), .cpopResult(cpopResult));
-
-  //byte instructions
+  //byte results
   logic [WIDTH-1:0] OrcBResult;
   logic [WIDTH-1:0] Rev8Result;
 
-  genvar i;
+  cnt cnt(.A(A), .W64(W64), .clzResult(clzResult), .ctzResult(ctzResult), .cpopResult(cpopResult));
 
-  for (i=0;i<WIDTH;i+=8) begin:loop
-    assign OrcBResult[i+7:i] = {8{|A[i+7:i]}};
-    assign Rev8Result[WIDTH-i:WIDTH-i-7] = A[i+7:i];
-  end
+  byteUnit bu(.A(A), .OrcBResult(OrcBResult), .Rev8Result(Rev8Result));
 
   //can replace with structural mux by looking at bit 4 in rs2 field
   always_comb begin