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Merge branch 'main' of github.com:openhwgroup/cvw

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This commit is contained in:
Jacob Pease 2023-09-06 10:52:08 -05:00
commit 257c8e481f
4 changed files with 13 additions and 7 deletions
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2
benchmarks/embench/Makefile
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@ -5,7 +5,7 @@
embench_dir = ../../addins/embench-iot
all: build
run: size sim
run: build size sim
allClean: clean all

4
src/cache/cachefsm.sv vendored
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@ -171,9 +171,9 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
assign ClearValid = P.ZICBOM_SUPPORTED & ((CurrState == STATE_READY & CMOp[0] & CacheHit) |
(CurrState == STATE_CMO_WRITEBACK & CMOp[2] & CacheBusAck));
// coverage off -item e 1 -fecexprrow 8
assign LRUWriteEn = (CurrState == STATE_READY & (AnyHit | CMOZeroNoEviction)) |
assign LRUWriteEn = ((CurrState == STATE_READY & (AnyHit | CMOZeroNoEviction)) |
(P.ZICBOZ_SUPPORTED & CurrState == STATE_WRITEBACK & CMOp[3] & CacheBusAck) |
(CurrState == STATE_WRITE_LINE) & ~FlushStage;
(CurrState == STATE_WRITE_LINE)) & ~FlushStage;
// exclusion-tag-start: icache flushdirtycontrols
assign SetDirty = (CurrState == STATE_READY & (AnyUpdateHit | CMOZeroNoEviction)) | // exclusion-tag: icache SetDirty
(CurrState == STATE_WRITE_LINE & (CacheRW[0])) |

4
src/ifu/ifu.sv
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@ -144,8 +144,8 @@ module ifu import cvw::*; #(parameter cvw_t P) (
/////////////////////////////////////////////////////////////////////////////////////////////
if(P.C_SUPPORTED) begin : Spill
spill #(P) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF,
.InstrUpdateDAF, .IFUCacheBusStallF, .ITLBMissF, .PCSpillNextF, .PCSpillF, .SelSpillNextF, .PostSpillInstrRawF, .CompressedF);
spill #(P) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF, .InstrUpdateDAF, .CacheableF,
.IFUCacheBusStallF, .ITLBMissF, .PCSpillNextF, .PCSpillF, .SelSpillNextF, .PostSpillInstrRawF, .CompressedF);
end else begin : NoSpill
assign PCSpillNextF = PCNextF;
assign PCSpillF = PCF;

10
src/ifu/spill.sv
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@ -40,6 +40,7 @@ module spill import cvw::*; #(parameter cvw_t P) (
input logic IFUCacheBusStallF, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched
input logic ITLBMissF, // ITLB miss, ignore memory request
input logic InstrUpdateDAF, // Ignore memory request if the hptw support write and a DA page fault occurs (hptw is still active)
input logic CacheableF, // Is the instruction from the cache?
output logic [P.XLEN-1:0] PCSpillNextF, // The next PCF for one of the two memory addresses of the spill
output logic [P.XLEN-1:0] PCSpillF, // PCF for one of the two memory addresses of the spill
output logic SelSpillNextF, // During the transition between the two spill operations, the IFU should stall the pipeline
@ -48,7 +49,6 @@ module spill import cvw::*; #(parameter cvw_t P) (
// Spill threshold occurs when all the cache offset PC bits are 1 (except [0]). Without a cache this is just PCF[1]
typedef enum logic [1:0] {STATE_READY, STATE_SPILL} statetype;
localparam SPILLTHRESHOLD = P.ICACHE_SUPPORTED ? P.ICACHE_LINELENINBITS/32 : 1;
statetype CurrState, NextState;
logic [P.XLEN-1:0] PCPlus2NextF, PCPlus2F;
@ -76,7 +76,13 @@ module spill import cvw::*; #(parameter cvw_t P) (
// Detect spill
////////////////////////////////////////////////////////////////////////////////////////////////////
assign SpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1];
if (P.ICACHE_SUPPORTED) begin
logic SpillCachedF, SpillUncachedF;
assign SpillCachedF = &PCF[$clog2(P.ICACHE_LINELENINBITS/32)+1:1];
assign SpillUncachedF = PCF[1]; // *** try to optimize this based on whether the next instruction is 16 bits and by fetching 64 bits in RV64
assign SpillF = CacheableF ? SpillCachedF : SpillUncachedF;
end else
assign SpillF = PCF[1]; // *** might relax - only spill if next instruction is uncompressed
assign TakeSpillF = SpillF & ~IFUCacheBusStallF & ~(ITLBMissF | (P.SVADU_SUPPORTED & InstrUpdateDAF));
always_ff @(posedge clk)