From 255332115834fe24b68e9ece68270027ef40061e Mon Sep 17 00:00:00 2001 From: Alec Vercruysse Date: Tue, 4 Apr 2023 22:20:31 -0700 Subject: [PATCH] fix typo in cachway setValid input comment --- src/cache/cacheway.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index d7cc0792d..c5660bf49 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -38,7 +38,7 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, input logic [$clog2(NUMLINES)-1:0] CacheSet, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr input logic [`PA_BITS-1:0] PAdr, // Physical address input logic [LINELEN-1:0] LineWriteData, // Final data written to cache (D$ only) - input logic SetValid, // Set the dirty bit in the selected way and set + input logic SetValid, // Set the valid bit in the selected way and set input logic ClearValid, // Clear the valid bit in the selected way and set input logic SetDirty, // Set the dirty bit in the selected way and set input logic ClearDirty, // Clear the dirty bit in the selected way and set