Merge branch 'main' of https://github.com/openhwgroup/cvw

sim/coverage-exclusions-rv64gc.do

@@ -119,13 +119,31 @@ coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/clintdec -lin
 set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"]
 coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uncoreramdec -linerange $line-$line -item e 1 -fecexprrow 5
 
-# Excluding signals in lsu: the lsu never executes instructions so 'ExecuteAccess' will never be 1
+## Excluding signals in lsu: the lsu never executes instructions so 'ExecuteAccessF' will never be 1
+# in pmachecker.sv
 set line [GetLineNum ../src/mmu/pmachecker.sv "AccessRWX ="]
 coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 6
 set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"]
 coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 4
+set line [GetLineNum ../src/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"]
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2
 
-# Excluding ReadAccess and WriteAccess signal in the ifu that will never be true
+# in mmu.sv
+set line [GetLineNum ../src/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"]
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 2
+set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"]
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
+set line [GetLineNum ../src/mmu/mmu.sv "PMAInstrAccessFaultF    \\|"]
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6
+
+# in pmpchecker.sv
+set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ExecuteAccessF"]
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6
+
+
+## Excluding ReadAccessM_1 and WriteAccessM_1 signals in the ifu pmachecker, mmu, pmpchecker because they will never be high 
+## and Excluding ExecuteAccessF_0 because it is always true/high in the ifu
+# in pmachecker.sv
 set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| WriteAccessM"]
 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 4
 set line [GetLineNum ../src/mmu/pmachecker.sv "WriteAccessM \\| ExecuteAccessF"]
@@ -133,6 +151,53 @@ coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$lin
 set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"]
 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-3
 
+set line [GetLineNum ../src/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"]
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1
+set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM    & PMAAccessFault"]
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2-4
+set line [GetLineNum ../src/mmu/pmachecker.sv "WriteAccessM   & PMAAccessFault"] 
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2-4
+set line [GetLineNum ../src/mmu/pmachecker.sv "AccessRWX \\| AtomicAccessM"] 
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 3
+
+# in mmu.sv
+set line [GetLineNum ../src/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"] 
+coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,3,4
+set line [GetLineNum ../src/mmu/mmu.sv "ReadAccessM & ~WriteAccessM"] 
+coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2-4
+set line [GetLineNum ../src/mmu/mmu.sv "DataMisalignedM & WriteAccessM"] 
+coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
+set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"] 
+coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 3
+set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ReadNoAmoAccessM"] 
+coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
+set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & WriteAccessM"] 
+coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
+set line [GetLineNum ../src/mmu/mmu.sv "DataMisalignedM & ReadNoAmoAccessM"] 
+coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
+
+# in pmpchecker.sv
+set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & WriteAccessM"] 
+coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6
+set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ReadAccessM"] 
+coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6
+
+## Executing any LoadAccess or StoreAccess signal in the ifu - depend on Read and Write Access that the ifu will never have
+# in /mmu/mmu.sv
+set line [GetLineNum ../src/mmu/mmu.sv "PMALoadAccessFaultM     \\| PMPLoadAccessFaultM"] 
+coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6
+set line [GetLineNum ../src/mmu/mmu.sv "PMAStoreAmoAccessFaultM \\| PMPStoreAmoAccessFaultM"] 
+coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6
+
+## Excluding ReadAccess_0, WriteAcess_1 in the TLB because the itlb only reads, and does not write
+set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "ReadAccess \\| WriteAccess"] 
+coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 1,3,4
+set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "CAMHit & TLBAccess"] 
+coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 3
+set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "~CAMHit & TLBAccess"] 
+coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 3
+
 # Excluding reset and clear for impossible case in the wficountreg in privdec
 set line [GetLineNum ../src/generic/flop/floprc.sv "reset \\| clear"]
 coverage exclude -scope /dut/core/priv/priv/pmd/wfi/wficountreg -linerange $line-$line -item c 1 -feccondrow 2
+

src/fpu/unpackinput.sv

@@ -303,8 +303,8 @@ module unpackinput (
   assign Man = {ExpNonZero, Frac}; // add the assumed one (or zero if Subnormal or zero) to create the significand
   assign NaN = ((ExpMax & ~FracZero)|BadNaNBox)&En; // is the input a NaN?
   assign SNaN = NaN&~Frac[`NF-1]&~BadNaNBox; // is the input a singnaling NaN?
-  assign Inf = ExpMax & FracZero &En & ~BadNaNBox; // is the input infinity?
+  assign Inf = ExpMax & FracZero & En; // is the input infinity?
-  assign Zero = ~ExpNonZero & FracZero & ~BadNaNBox; // is the input zero?
+  assign Zero = ~ExpNonZero & FracZero; // is the input zero?
   assign Subnorm = ~ExpNonZero & ~FracZero & ~BadNaNBox; // is the input subnormal
 
 endmodule

src/privileged/privdec.sv

@@ -69,7 +69,10 @@ module privdec (
     logic [`WFI_TIMEOUT_BIT:0] WFICount, WFICountPlus1;
     assign WFICountPlus1 = WFICount + 1;
     floprc #(`WFI_TIMEOUT_BIT+1) wficountreg(clk, reset, ~wfiM, WFICountPlus1, WFICount);  // count while in WFI
+  // coverage off -item e 1 -fecexprrow 1
+  // WFI Timout trap will not occur when STATUS_TW is low while in supervisor mode, so the system gets stuck waiting for an interrupt and triggers a watchdog timeout.
     assign WFITimeoutM = ((STATUS_TW & PrivilegeModeW != `M_MODE) | (`S_SUPPORTED & PrivilegeModeW == `U_MODE)) & WFICount[`WFI_TIMEOUT_BIT]; 
+  // coverage on
   end else assign WFITimeoutM = 0;
 
   ///////////////////////////////////////////

testbench/tests.vh

@@ -52,18 +52,18 @@ string tvpaths[] = '{
     "fpu",
     "lsu",
     "vm64check",
-    "pmp",
-    "dcache1",
-    "dcache2",
-    "pmpcfg",
-    "pmpcfg1",
-    "pmpcfg2",
-    "tlbKP",
-    "tlbMP",
-    "tlbM3",
     "tlbASID",
     "tlbGLB",
-    "ifuCamlineWrite"
+    "tlbMP",
+    "tlbGP",
+    "tlbTP",
+    "ifuCamlineWrite",
+    "dcache1",
+    "dcache2",
+    "pmp",
+    "pmpcfg",
+    "pmpcfg1",
+    "pmpcfg2"
   };
 
   string coremark[] = '{

tests/coverage/priv.S

@@ -169,6 +169,24 @@ main:
     csrw mcounteren, t0
     csrw scounteren, t0
 
+    #getting the remainder of PMD instructions
+
+    #go to user mode
+    li a0, 0
+    ecall
+    #set status TVM to 0 by writing to bit 20 of mstatus as 0
+    #bseti t0, zero, 20 
+    sfence.vma zero, zero
+
+    # Go to supervisor mode
+    li a0, 1
+    ecall
+
+    sfence.vma zero, zero
+
+    li a0, 3
+    ecall
+
     # Write to satp when status.TVM is 1 from machine mode
     bseti t0, zero, 20 
     csrs mstatus, t0
@@ -203,6 +221,30 @@ main:
 
     csrr t0, hpmcounter22
 
+    #getting the mpp and mstatus Mpriv condition met
+    #go to machine mode
+    li a0, 3
+    ecall
+    # set bit 17 of mstatus to enable STATUS_MPRV
+    bseti t1, zero, 17
+    csrs mstatus, t1
+
+    li a0, 3
+    ecall
+
+    # set bit 21 of mstatus to 0 to disable STATUS_TW
+    csrr t1, mstatus
+    bseti t2, zero, 21
+    not t2, t2
+    and t1, t1, t2
+    csrs mstatus, t1
+
+    # go to user mode
+    li a0, 0
+    ecall
+
+    wfi
+
     j done
 
 

tests/coverage/tlbASID.S

@@ -46,26 +46,21 @@ main:
     li t5, 0            # j = 0 // now use as a counter for new asid loop 
     li t3, 32     # Max amount of Loops = 32
 
-loop: bge t2, t3, nASID   # exit loop if i >= loops
+loop: bge t2, t3, finished   # exit loop if i >= loops
-    lw t1, 0(t0)
+    li t1, 0x00008067 #load in jalr
+    sw t1, 0(t0)
+    fence.I
+    jalr t0
+    li t5, 0x9001000000080080 // try making asid = 1 
+    csrw satp, t5
+    jalr t0
+     li t5, 0x9000000000080080 // try making asid = 0
+    csrw satp, t5
     li t4, 0x1000
     add t0, t0, t4
     addi t2, t2, 1
     j loop
     
-nASID: bne t5, zero, finished
-    li a0, 3   // go
-    ecall
-    li t5, 0x9000100000080080 // try making asid = 1 
-    csrw satp, t5
-    li a0, 1   
-    ecall
-    li t2, 0
-    li t0, 0xC0000000
-    li t5, 1 // make this not zero. 
-    j loop
-
-
 finished:
     j done
 

tests/coverage/tlbGLB.S

@@ -48,7 +48,10 @@ main:
     li t3, 32     # Max amount of Loops = 32
 
 loop: bge t2, t3, nASID   # exit loop if i >= loops
-    lw t1, 0(t0)
+    li t1, 0x00008067 #load in jalr
+    sw t1, 0(t0)
+    fence.I
+    jalr t0
     li t4, 0x1000
     add t0, t0, t4
     addi t2, t2, 1
@@ -79,17 +82,57 @@ pagetable:
 .align 12 // level 2 page table, contains direction to a gigapageg
     .8byte 0x0
     .8byte 0x0
-    .8byte 0x200000CF // gigapage that starts at 8000 0000 goes to C000 0000
+    .8byte 0x200000EF // gigapage that starts at 8000 0000 goes to C000 0000
-    .8byte 0x200208C1 // pointer to next page table entry at 8008 2000
+    .8byte 0x200208E1 // pointer to next page table entry at 8008 2000
 
 .align 12 // level 1 page table, points to level 0 page table
     .8byte 0x20020CE1
 
 .align 12 // level 0 page table, points to address C000 0000 // FOR NOW ALL OF THESE GO TO 8 instead of C cause they start with 2
-    .8byte 0x200000CF // access xC000 0000
+    .8byte 0x200000EF // access xC000 0000
-    .8byte 0x200004CF // access xC000 1000
+    .8byte 0x200004EF // access xC000 1000
-    .8byte 0x200008CF // access xC000 2000
+    .8byte 0x200008EF // access xC000 2000
-    .8byte 0x20000CCF // access xC000 3000
+    .8byte 0x20000CEF // access xC000 3000
+
+    .8byte 0x200010EF // access xC000 4000
+    .8byte 0x200014EF
+    .8byte 0x200018EF
+    .8byte 0x20001CEF
+
+    .8byte 0x200020EF // access xC000 8000
+    .8byte 0x200024EF
+    .8byte 0x200028EF
+    .8byte 0x20002CEF
+
+    .8byte 0x200030EF // access xC000 C000
+    .8byte 0x200034EF
+    .8byte 0x200038EF
+    .8byte 0x20003CEF
+
+    .8byte 0x200040EF // access xC001 0000
+    .8byte 0x200044EF
+    .8byte 0x200048EF
+    .8byte 0x20004CEF
+
+    .8byte 0x200050EF // access xC001 4000
+    .8byte 0x200054EF
+    .8byte 0x200058EF
+    .8byte 0x20005CEF
+
+    .8byte 0x200060EF // access xC001 8000
+    .8byte 0x200064EF
+    .8byte 0x200068EF
+    .8byte 0x20006CEF
+
+    .8byte 0x200070EF // access xC001 C000
+    .8byte 0x200074eF
+    .8byte 0x200078EF
+    .8byte 0x20007CEF
+
+    .8byte 0x200080EF // access xC002 0000
+    .8byte 0x200084EF
+    .8byte 0x200088EF
+    .8byte 0x20008CEF
 
         .8byte 0x200010EF // access xC000 4000
     .8byte 0x200014EF
@@ -132,3 +175,5 @@ pagetable:
     .8byte 0x20008CEF
 
 
+
+    

tests/coverage/tlbGP.S

@@ -0,0 +1,158 @@
+///////////////////////////////////////////
+// tlbGP.S
+//
+// Written: mmendozamanriquez@hmc.edu 4 April 2023
+//          nlimpert@hmc.edu
+//
+// Purpose: Create Page tables and access gigapages
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// load code to initalize stack, handle interrupts, terminate
+
+#include "WALLY-init-lib.h"
+
+# run-elf.bash find this in project description
+main:
+    # Page table root address at 0x80010000
+    li t5, 0x9000000000080010
+    csrw satp, t5
+
+    # sfence.vma x0, x0
+
+    # switch to supervisor mode
+    li a0, 1   
+    ecall
+    li t5, 0 
+    li t0, 0xC0200000 // go to first gigapage 
+    li t4, 0x40000000 // put this outside the loop.
+    li t2, 0      # i = 0
+    li t3, 64     # Max amount of Loops = 16
+
+loop: bge t2, t3, finished   # exit loop if i >= loops
+    lw t1, 0(t0)
+    li t1, 0x00008067 #load in jalr
+    sw t1, 0(t0)
+    fence.I
+    jalr t0
+    add t0, t0, t4
+    addi t2, t2, 1
+    j loop
+
+finished:
+    j done
+
+.data
+
+.align 16
+# Page table situated at 0x80010000
+pagetable: 
+    .8byte 0x200044C1
+
+.align 12 
+    .8byte 0x000000CF  //8000 0000
+    .8byte 0x100000CF
+    .8byte 0x200000CF  
+    .8byte 0x200000CF  
+
+    .8byte 0x200000CF
+    .8byte 0x200000CF
+    .8byte 0x200000CF
+    .8byte 0x200000CF  
+ 
+    .8byte 0x200000CF
+    .8byte 0x200000CF 
+    .8byte 0x200000CF
+    .8byte 0x200000CF  
+
+    .8byte 0x200000CF
+    .8byte 0x200000CF
+    .8byte 0x200000CF 
+    .8byte 0x200000CF  
+
+    .8byte 0x200000CF  
+    .8byte 0x200000CF
+    .8byte 0x200000CF  
+    .8byte 0x200000CF  
+
+    .8byte 0x200000CF
+    .8byte 0x200000CF
+    .8byte 0x200000CF
+    .8byte 0x200000CF  
+ 
+    .8byte 0x200000CF
+    .8byte 0x200000CF 
+    .8byte 0x200000CF
+    .8byte 0x200000CF  
+
+    .8byte 0x200000CF
+    .8byte 0x200000CF
+    .8byte 0x200000CF 
+    .8byte 0x200000CF  
+
+    .8byte 0x200000CF  
+    .8byte 0x200000CF
+    .8byte 0x200000CF  
+    .8byte 0x200000CF  
+
+    .8byte 0x200000CF
+    .8byte 0x200000CF
+    .8byte 0x200000CF
+    .8byte 0x200000CF  
+ 
+    .8byte 0x200000CF
+    .8byte 0x200000CF 
+    .8byte 0x200000CF
+    .8byte 0x200000CF  
+
+    .8byte 0x200000CF
+    .8byte 0x200000CF
+    .8byte 0x200000CF 
+    .8byte 0x200000CF  
+
+    .8byte 0x200000CF  
+    .8byte 0x200000CF
+    .8byte 0x200000CF  
+    .8byte 0x200000CF  
+
+    .8byte 0x200000CF
+    .8byte 0x200000CF
+    .8byte 0x200000CF
+    .8byte 0x200000CF  
+ 
+    .8byte 0x200000CF
+    .8byte 0x200000CF 
+    .8byte 0x200000CF
+    .8byte 0x200000CF  
+
+    .8byte 0x200000CF
+    .8byte 0x200000CF
+    .8byte 0x200000CF 
+    .8byte 0x200000CF  
+
+
+    .8byte 0x200000CF
+    .8byte 0x200000CF
+    .8byte 0x200000CF 
+    .8byte 0x200000CF 
+
+
+
+
+    

tests/coverage/tlbMP.S

@@ -39,25 +39,22 @@ main:
     # switch to supervisor mode
     li a0, 1   
     ecall
+
     li t5, 0 
     li t0, 0x84000000 // go to first megapage
-    li t4, 0x1000 // put this outside the loop.
+    li t4, 0x200000 // put this outside the loop.
     li t2, 0      # i = 0
     li t3, 32     # Max amount of Loops = 16
 
-loop: bge t2, t3, lKP   # exit loop if i >= loops
+loop: bge t2, t3, finished   # exit loop if i >= loops
-    lw t1, 0(t0)
+    li t1, 0x00008067 #load in jalr
+    sw t1, 0(t0)
+    fence.I
+    jalr t0
     add t0, t0, t4
     addi t2, t2, 1
     j loop
 
-lKP: bne t5, zero, finished
-    li t0, 0x80000000 
-    slli t4, t4, 9
-    addi t5, t5, 1
-    li t2, 0
-    j loop
-
 finished:
     j done
 
@@ -116,6 +113,46 @@ pagetable:
     .8byte 0x20F000CF 
     .8byte 0x20F800CF
 
+    .8byte 0x200000CF // access 8000,0000 I AM REPEATING PTE TO SAVE TIME.
+    .8byte 0x200800CF // access 8020,0000 
+    .8byte 0x201000CF // acesss 8040,0000
+    .8byte 0x201800CF // acesss 8060,0000
+
+    .8byte 0x202000CF // access 8080,0000
+    .8byte 0x202800CF // access 80A0,0000
+    .8byte 0x203000CF // access 80C0,0000
+    .8byte 0x203800CF // access 80E0,0000
+
+    .8byte 0x204000CF // access 8100,0000
+    .8byte 0x204800CF 
+    .8byte 0x205000CF 
+    .8byte 0x205800CF 
+
+    .8byte 0x206000CF // access 8180,0000
+    .8byte 0x206800CF 
+    .8byte 0x207000CF 
+    .8byte 0x207800CF 
+
+    .8byte 0x208000CF // access 8200,0000
+    .8byte 0x208800CF 
+    .8byte 0x209000CF 
+    .8byte 0x209800CF 
+
+    .8byte 0x20A000CF // access 8280,0000
+    .8byte 0x20A800CF 
+    .8byte 0x20B000CF 
+    .8byte 0x20B800CF 
+
+    .8byte 0x20C000CF // access 8300,0000
+    .8byte 0x20C800CF 
+    .8byte 0x20D000CF 
+    .8byte 0x20D800CF
+
+    .8byte 0x20E000CF // access 8380,0000
+    .8byte 0x20E800CF 
+    .8byte 0x20F000CF 
+    .8byte 0x20F800CF
+
     .8byte 0x20004CC1
      // Kilopage entry, for addresses from 8400, 0000 to 841F, FFFF
                       // point to ... 

tests/coverage/tlbTP.S

@@ -0,0 +1,144 @@
+///////////////////////////////////////////
+// tlbTP.S
+//
+// Written: mmendozamanriquez@hmc.edu 4 April 2023
+//          nlimpert@hmc.edu
+//
+// Purpose: Test coverage for LSU
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// load code to initalize stack, handle interrupts, terminate
+
+#include "WALLY-init-lib.h"
+
+# run-elf.bash find this in project description
+main:
+    # Page table root address at 0x80010000
+    li t5, 0x9000000000080010
+    csrw satp, t5
+
+    # sfence.vma x0, x0
+
+    # switch to supervisor mode
+    li a0, 1   
+    ecall
+    li t5, 0 
+    li t0, 0x80000000 // go to first gigapage 
+    li t4, 0x8000000000 // put this outside the loop.
+    li t2, 0      # i = 0
+    li t3, 64     # run through 64 PTEs
+
+loop: bge t2, t3, finished   # exit loop if i >= loops
+    li t1, 0x00008067
+    sw t1, 0(t0)
+    fence.I
+    jalr t0
+    add t0, t0, t4
+    addi t2, t2, 1
+    j loop
+
+
+finished:
+    j done
+
+.data
+
+.align 16
+# Page table situated at 0x80010000
+pagetable: 
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF
+    .8byte 0x0CF