From 726c17034b9a6ef0278a46e4e16b2ea7c57a8357 Mon Sep 17 00:00:00 2001
From: davidharrishmc <74973295+davidharrishmc@users.noreply.github.com>
Date: Wed, 27 Oct 2021 10:41:37 -0700
Subject: [PATCH] Added instructions for making rv32if device

---
 README.md | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/README.md b/README.md
index 559c3e0ee..420ea87a1 100644
--- a/README.md
+++ b/README.md
@@ -14,6 +14,8 @@ cd ../addins
 git clone https://github.com/riscv-non-isa/riscv-arch-test
 git clone https://github.com/riscv-software-src/riscv-isa-sim
 cd riscv-isa-sim
+cp -r arch_test_target/spike/device/rv32i_m/I arch_test_target/spike/device/rv32i_m/F
+<edit arch_test_target/spike/device/rv32i_m/F/Makefile.include line 35 and change --isa=rv32i to --isa=rv32if>
 mkdir build
 cd build
 set RISCV=/cad/riscv/gcc/bin   (or whatever your path is)