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busybear: more progress moving from instrf to instrrawd
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parent
f3194c6388
commit
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@ -262,7 +262,7 @@ module testbench_busybear();
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end
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end
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always @(dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW) begin
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always @(dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW) begin
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if (dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW == 2 && instrs != 0) begin
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if (dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW == 2 && instrs > 1) begin
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$display("!!!!!! illegal instruction !!!!!!!!!!");
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$display("!!!!!! illegal instruction !!!!!!!!!!");
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$display("(as a reminder, MCAUSE and MEPC are set by this)");
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$display("(as a reminder, MCAUSE and MEPC are set by this)");
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$display("at %0t ps, instr %0d, HADDR %x", $time, instrs, HADDR);
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$display("at %0t ps, instr %0d, HADDR %x", $time, instrs, HADDR);
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@ -282,7 +282,7 @@ module testbench_busybear();
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//CSR checking \
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//CSR checking \
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always @(``PATH``.``CSR``_REGW) begin \
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always @(``PATH``.``CSR``_REGW) begin \
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if ($time > 1) begin \
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if ($time > 1) begin \
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if (instrs != 0) begin \
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if (instrs > 1) begin \
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scan_file_csr = $fscanf(data_file_csr, "%s\n", CSR); \
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scan_file_csr = $fscanf(data_file_csr, "%s\n", CSR); \
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scan_file_csr = $fscanf(data_file_csr, "%x\n", expected``CSR``); \
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scan_file_csr = $fscanf(data_file_csr, "%x\n", expected``CSR``); \
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if(CSR.icompare(`"CSR`")) begin \
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if(CSR.icompare(`"CSR`")) begin \
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@ -385,7 +385,7 @@ module testbench_busybear();
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always @(dut.hart.ifu.PCD or dut.hart.ifu.InstrRawD or reset) begin
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always @(dut.hart.ifu.PCD or dut.hart.ifu.InstrRawD or reset) begin
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if(~HWRITE) begin
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if(~HWRITE) begin
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#3;
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#3;
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if (~reset && dut.hart.ifu.InstrRawD[15:0] !== {16{1'bx}} && ~dut.hart.StallD) begin
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if (~reset && dut.hart.ifu.InstrRawD[15:0] !== {16{1'bx}} && dut.hart.ifu.PCD !== 64'h0) begin
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if (dut.hart.ifu.PCD !== lastPCD) begin
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if (dut.hart.ifu.PCD !== lastPCD) begin
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lastCheckInstrD = CheckInstrD;
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lastCheckInstrD = CheckInstrD;
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lastPC <= dut.hart.ifu.PCD;
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lastPC <= dut.hart.ifu.PCD;
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