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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

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This commit is contained in:
David Harris 2022-08-25 09:52:49 -07:00
commit 24ce72f0a2
16 changed files with 267 additions and 278 deletions
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39
fpga/constraints/debug2.xdc
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File diff suppressed because one or more lines are too long

60
fpga/generator/wave_config.wcfg
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@ -10,12 +10,12 @@
</db_ref_list> </db_ref_list>
<zoom_setting> <zoom_setting>
<ZoomStartTime time="0fs"></ZoomStartTime> <ZoomStartTime time="0fs"></ZoomStartTime>
<ZoomEndTime time="168fs"></ZoomEndTime> <ZoomEndTime time="3838fs"></ZoomEndTime>
<Cursor1Time time="0fs"></Cursor1Time> <Cursor1Time time="0fs"></Cursor1Time>
</zoom_setting> </zoom_setting>
<column_width_setting> <column_width_setting>
<NameColumnWidth column_width="452"></NameColumnWidth> <NameColumnWidth column_width="452"></NameColumnWidth>
<ValueColumnWidth column_width="141"></ValueColumnWidth> <ValueColumnWidth column_width="133"></ValueColumnWidth>
</column_width_setting> </column_width_setting>
<WVObjectSize size="11" /> <WVObjectSize size="11" />
<wave_markers> <wave_markers>
@ -69,14 +69,6 @@
<obj_property name="LABELRADIX">true</obj_property> <obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property> <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject> </wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/core/ReadDataM">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/ReadDataM[63:0]</obj_property>
<obj_property name="ObjectShortName">ReadDataM[63:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/WriteDataM"> <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/WriteDataM">
<obj_property name="DisplayName">FullPathName</obj_property> <obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/WriteDataM[63:0]</obj_property> <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/WriteDataM[63:0]</obj_property>
@ -98,14 +90,6 @@
<obj_property name="LABELRADIX">true</obj_property> <obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property> <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject> </wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/trap/SIP_REGW">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/SIP_REGW[9:9]</obj_property>
<obj_property name="ObjectShortName">SIP_REGW[9:9]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
</wvobject> </wvobject>
<wvobject type="group" fp_name="group470"> <wvobject type="group" fp_name="group470">
<obj_property name="label">PLIC</obj_property> <obj_property name="label">PLIC</obj_property>
@ -148,22 +132,6 @@
<obj_property name="ObjectShortName">MIDELEG_REGW[11:0]</obj_property> <obj_property name="ObjectShortName">MIDELEG_REGW[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property> <obj_property name="Radix">HEXRADIX</obj_property>
</wvobject> </wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[11:0]</obj_property>
<obj_property name="ObjectShortName">MPendingIntsM[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[11:0]</obj_property>
<obj_property name="ObjectShortName">SPendingIntsM[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/InterruptM"> <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/InterruptM">
<obj_property name="DisplayName">FullPathName</obj_property> <obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/InterruptM</obj_property> <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/InterruptM</obj_property>
@ -280,30 +248,6 @@
<obj_property name="LABELRADIX">true</obj_property> <obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property> <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject> </wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/trap/SIE_REGW">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/SIE_REGW[9:9]</obj_property>
<obj_property name="ObjectShortName">SIE_REGW[9:9]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/trap/SIE_REGW_1">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/SIE_REGW_1[1:1]</obj_property>
<obj_property name="ObjectShortName">SIE_REGW_1[1:1]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/trap/SIE_REGW_2">
<obj_property name="DisplayName">FullPathName</obj_property>
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/SIE_REGW_2[5:5]</obj_property>
<obj_property name="ObjectShortName">SIE_REGW_2[5:5]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
<obj_property name="LABELRADIX">true</obj_property>
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
</wvobject>
</wvobject> </wvobject>
<wvobject type="group" fp_name="group487"> <wvobject type="group" fp_name="group487">
<obj_property name="label">sdc</obj_property> <obj_property name="label">sdc</obj_property>

40
pipelined/regression/fpga-wave.do
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@ -168,26 +168,26 @@ add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/Load
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
add wave -noupdate -expand -group AHB -color Gold /testbench/dut/core/ebu/BusState add wave -noupdate -expand -group AHB -color Gold /testbench/dut/core/ebu/ebu/BusState
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/NextBusState add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/NextBusState
add wave -noupdate -expand -group AHB -expand -group {input requests} /testbench/dut/core/ebu/AtomicMaskedM add wave -noupdate -expand -group AHB -expand -group {input requests} /testbench/dut/core/ebu/ebu/AtomicMaskedM
add wave -noupdate -expand -group AHB -expand -group {input requests} /testbench/dut/core/ebu/LSUBusSize add wave -noupdate -expand -group AHB -expand -group {input requests} /testbench/dut/core/ebu/ebu/LSUBusSize
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HCLK add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HCLK
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HRESETn add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HRESETn
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HRDATA add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HRDATA
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HREADY add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HREADY
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HRESP add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HRESP
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HADDR add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HADDR
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HWDATA add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HWDATA
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HWRITE add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HWRITE
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HSIZE add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HSIZE
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HBURST add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HBURST
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HPROT add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HPROT
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HTRANS add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HTRANS
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HMASTLOCK add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HADDRD add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HADDRD
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HSIZED add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HSIZED
add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/HWRITED add wave -noupdate -expand -group AHB /testbench/dut/core/ebu/ebu/HWRITED
add wave -noupdate -expand -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState add wave -noupdate -expand -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/InterlockStall add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/InterlockStall

38
pipelined/regression/linux-wave.do
View File

@ -389,25 +389,25 @@ add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group typ
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/ITLBMissOrDAFaultF add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/ITLBMissOrDAFaultF
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM
add wave -noupdate -group AHB -color Gold /testbench/dut/core/ebu/BusState add wave -noupdate -group AHB -color Gold /testbench/dut/core/ebu/ebu/BusState
add wave -noupdate -group AHB /testbench/dut/core/ebu/NextBusState add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/NextBusState
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/AtomicMaskedM add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/ebu/AtomicMaskedM
add wave -noupdate -group AHB /testbench/dut/core/ebu/HCLK add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HCLK
add wave -noupdate -group AHB /testbench/dut/core/ebu/HRESETn add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESETn
add wave -noupdate -group AHB /testbench/dut/core/ebu/HRDATA add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRDATA
add wave -noupdate -group AHB /testbench/dut/core/ebu/HREADY add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HREADY
add wave -noupdate -group AHB /testbench/dut/core/ebu/HRESP add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESP
add wave -noupdate -group AHB /testbench/dut/core/ebu/HADDR add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HADDR
add wave -noupdate -group AHB /testbench/dut/core/ebu/HWDATA add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWDATA
add wave -noupdate -group AHB /testbench/dut/core/ebu/HWRITE add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWRITE
add wave -noupdate -group AHB /testbench/dut/core/ebu/HSIZE add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HSIZE
add wave -noupdate -group AHB /testbench/dut/core/ebu/HBURST add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
add wave -noupdate -group AHB /testbench/dut/core/ebu/HPROT add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT
add wave -noupdate -group AHB /testbench/dut/core/ebu/HTRANS add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
add wave -noupdate -group AHB /testbench/dut/core/ebu/HMASTLOCK add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
add wave -noupdate -group AHB /testbench/dut/core/ebu/HADDRD add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HADDRD
add wave -noupdate -group AHB /testbench/dut/core/ebu/HSIZED add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HSIZED
add wave -noupdate -group AHB /testbench/dut/core/ebu/HWRITED add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWRITED
add wave -noupdate -group AHB -group {pc selection} /testbench/dut/core/ifu/PCNext2F add wave -noupdate -group AHB -group {pc selection} /testbench/dut/core/ifu/PCNext2F
add wave -noupdate -group AHB -group {pc selection} /testbench/dut/core/ifu/PrivilegedNextPCM add wave -noupdate -group AHB -group {pc selection} /testbench/dut/core/ifu/PrivilegedNextPCM
add wave -noupdate -group AHB -group {pc selection} /testbench/dut/core/ifu/PrivilegedChangePCM add wave -noupdate -group AHB -group {pc selection} /testbench/dut/core/ifu/PrivilegedChangePCM

82
pipelined/regression/wave-all.do
View File

@ -7,7 +7,7 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE
add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE
add wave -noupdate -divider <NULL> add wave -noupdate -divider <NULL>
add wave -noupdate /testbench/dut/core/ebu/IReadF add wave -noupdate /testbench/dut/core/ebu/ebu/IReadF
add wave -noupdate /testbench/dut/core/DataStall add wave -noupdate /testbench/dut/core/DataStall
add wave -noupdate /testbench/dut/core/InstrStall add wave -noupdate /testbench/dut/core/InstrStall
add wave -noupdate /testbench/dut/core/StallF add wave -noupdate /testbench/dut/core/StallF
@ -656,46 +656,46 @@ add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/rese
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/clear add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/clear
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/d add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/q add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/clk add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/reset add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/UnsignedLoadM add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/UnsignedLoadM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/InstrPAdrF add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/InstrPAdrF
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/IReadF add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/IReadF
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/IRData add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/IRData
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/MemPAdrM add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/MemPAdrM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/DReadM add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/DReadM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/DWriteM add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/DWriteM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/WriteDataM add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/WriteDataM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/DSizeM add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/DSizeM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/DRData add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/DRData
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HRDATA add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HRDATA
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HREADY add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HREADY
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HRESP add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HRESP
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HCLK add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HCLK
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HRESETn add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HRESETn
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HADDR add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HADDR
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HWDATA add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HWDATA
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HWRITE add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HWRITE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HSIZE add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HSIZE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HBURST add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HBURST
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HPROT add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HPROT
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HTRANS add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HTRANS
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HMASTLOCK add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HMASTLOCK
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/InstrAckD add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/InstrAckD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/MemAckW add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/MemAckW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/GrantData add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/GrantData
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ISize add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/ISize
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/HRDATAMasked add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HRDATAMasked
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/IReady add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/IReady
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/DReady add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/DReady
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/swr/HRDATA add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/HRDATA
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/swr/HADDR add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/HADDR
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/swr/UnsignedLoadM add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/UnsignedLoadM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/swr/HSIZE add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/HSIZE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/swr/HRDATAMasked add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/HRDATAMasked
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/swr/ByteM add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/ByteM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/swr/HalfwordM add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/HalfwordM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/swr/genblk1/WordM add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/genblk1/WordM
add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/PCSrcE add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/PCSrcE
add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/CSRWritePendingDEM add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/CSRWritePendingDEM
add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/RetM add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/RetM

28
pipelined/regression/wave-dos/ahb-muldiv.do
View File

@ -7,7 +7,7 @@ add wave /testbench/reset
add wave -divider add wave -divider
# new # new
#add wave /testbench/dut/core/ebu/IReadF #add wave /testbench/dut/core/ebu/ebu/IReadF
add wave /testbench/dut/core/DataStall add wave /testbench/dut/core/DataStall
add wave /testbench/dut/core/ICacheStallF add wave /testbench/dut/core/ICacheStallF
add wave /testbench/dut/core/StallF add wave /testbench/dut/core/StallF
@ -57,18 +57,18 @@ add wave -hex /testbench/dut/uncore/HADDR
add wave -hex /testbench/dut/uncore/HWDATA add wave -hex /testbench/dut/uncore/HWDATA
add wave -divider add wave -divider
add wave -hex /testbench/dut/core/ebu/MemReadM add wave -hex /testbench/dut/core/ebu/ebu/MemReadM
add wave -hex /testbench/dut/core/ebu/InstrReadF add wave -hex /testbench/dut/core/ebu/ebu/InstrReadF
add wave -hex /testbench/dut/core/ebu/BusState add wave -hex /testbench/dut/core/ebu/ebu/BusState
add wave -hex /testbench/dut/core/ebu/NextBusState add wave -hex /testbench/dut/core/ebu/ebu/NextBusState
add wave -hex /testbench/dut/core/ebu/HADDR add wave -hex /testbench/dut/core/ebu/ebu/HADDR
add wave -hex /testbench/dut/core/ebu/HREADY add wave -hex /testbench/dut/core/ebu/ebu/HREADY
add wave -hex /testbench/dut/core/ebu/HTRANS add wave -hex /testbench/dut/core/ebu/ebu/HTRANS
add wave -hex /testbench/dut/core/ebu/HRDATA add wave -hex /testbench/dut/core/ebu/ebu/HRDATA
add wave -hex /testbench/dut/core/ebu/HWRITE add wave -hex /testbench/dut/core/ebu/ebu/HWRITE
add wave -hex /testbench/dut/core/ebu/HWDATA add wave -hex /testbench/dut/core/ebu/ebu/HWDATA
add wave -hex /testbench/dut/core/ebu/HBURST add wave -hex /testbench/dut/core/ebu/ebu/HBURST
add wave -hex /testbench/dut/core/ebu/CaptureDataM add wave -hex /testbench/dut/core/ebu/ebu/CaptureDataM
add wave -divider add wave -divider
add wave -hex /testbench/dut/uncore/ram/* add wave -hex /testbench/dut/uncore/ram/*
@ -78,7 +78,7 @@ add wave -hex /testbench/dut/core/ifu/PCW
add wave -hex /testbench/dut/core/ifu/InstrW add wave -hex /testbench/dut/core/ifu/InstrW
add wave /testbench/InstrWName add wave /testbench/InstrWName
add wave /testbench/dut/core/ieu/dp/RegWriteW add wave /testbench/dut/core/ieu/dp/RegWriteW
add wave -hex /testbench/dut/core/ebu/ReadDataW add wave -hex /testbench/dut/core/ebu/ebu/ReadDataW
add wave -hex /testbench/dut/core/ieu/dp/ResultW add wave -hex /testbench/dut/core/ieu/dp/ResultW
add wave -hex /testbench/dut/core/ieu/dp/RdW add wave -hex /testbench/dut/core/ieu/dp/RdW
add wave -divider add wave -divider

26
pipelined/regression/wave-dos/ahb-waves.do
View File

@ -7,7 +7,7 @@ add wave /testbench/clk
add wave /testbench/reset add wave /testbench/reset
add wave -divider add wave -divider
#add wave /testbench/dut/core/ebu/IReadF #add wave /testbench/dut/core/ebu/ebu/IReadF
add wave /testbench/dut/core/DataStall add wave /testbench/dut/core/DataStall
add wave /testbench/dut/core/ICacheStallF add wave /testbench/dut/core/ICacheStallF
add wave /testbench/dut/core/StallF add wave /testbench/dut/core/StallF
@ -45,17 +45,17 @@ add wave -hex /testbench/dut/uncore/HADDR
add wave -hex /testbench/dut/uncore/HWDATA add wave -hex /testbench/dut/uncore/HWDATA
add wave -divider add wave -divider
add wave -hex /testbench/dut/core/ebu/MemReadM add wave -hex /testbench/dut/core/ebu/ebu/MemReadM
add wave -hex /testbench/dut/core/ebu/InstrReadF add wave -hex /testbench/dut/core/ebu/ebu/InstrReadF
add wave -hex /testbench/dut/core/ebu/BusState add wave -hex /testbench/dut/core/ebu/ebu/BusState
add wave -hex /testbench/dut/core/ebu/NextBusState add wave -hex /testbench/dut/core/ebu/ebu/NextBusState
add wave -hex /testbench/dut/core/ebu/HADDR add wave -hex /testbench/dut/core/ebu/ebu/HADDR
add wave -hex /testbench/dut/core/ebu/HREADY add wave -hex /testbench/dut/core/ebu/ebu/HREADY
add wave -hex /testbench/dut/core/ebu/HTRANS add wave -hex /testbench/dut/core/ebu/ebu/HTRANS
add wave -hex /testbench/dut/core/ebu/HRDATA add wave -hex /testbench/dut/core/ebu/ebu/HRDATA
add wave -hex /testbench/dut/core/ebu/HWRITE add wave -hex /testbench/dut/core/ebu/ebu/HWRITE
add wave -hex /testbench/dut/core/ebu/HWDATA add wave -hex /testbench/dut/core/ebu/ebu/HWDATA
add wave -hex /testbench/dut/core/ebu/CaptureDataM add wave -hex /testbench/dut/core/ebu/ebu/CaptureDataM
add wave -divider add wave -divider
add wave -hex /testbench/dut/uncore/ram/* add wave -hex /testbench/dut/uncore/ram/*
@ -65,7 +65,7 @@ add wave -hex /testbench/dut/core/ifu/PCW
add wave -hex /testbench/dut/core/ifu/InstrW add wave -hex /testbench/dut/core/ifu/InstrW
add wave /testbench/InstrWName add wave /testbench/InstrWName
add wave /testbench/dut/core/ieu/dp/RegWriteW add wave /testbench/dut/core/ieu/dp/RegWriteW
add wave -hex /testbench/dut/core/ebu/ReadDataW add wave -hex /testbench/dut/core/ebu/ebu/ReadDataW
add wave -hex /testbench/dut/core/ieu/dp/ResultW add wave -hex /testbench/dut/core/ieu/dp/ResultW
add wave -hex /testbench/dut/core/ieu/dp/RdW add wave -hex /testbench/dut/core/ieu/dp/RdW
add wave -divider add wave -divider

36
pipelined/regression/wave-dos/cache-waves.do
View File

@ -2,7 +2,7 @@ add wave /testbench/clk
add wave /testbench/reset add wave /testbench/reset
add wave -divider add wave -divider
#add wave /testbench/dut/core/ebu/IReadF #add wave /testbench/dut/core/ebu/ebu/IReadF
add wave /testbench/dut/core/DataStall add wave /testbench/dut/core/DataStall
add wave /testbench/dut/core/ICacheStallF add wave /testbench/dut/core/ICacheStallF
add wave /testbench/dut/core/StallF add wave /testbench/dut/core/StallF
@ -41,30 +41,30 @@ add wave -hex /testbench/dut/uncore/HADDR
add wave -hex /testbench/dut/uncore/HWDATA add wave -hex /testbench/dut/uncore/HWDATA
add wave -divider add wave -divider
add wave -hex /testbench/dut/core/ebu/MemReadM add wave -hex /testbench/dut/core/ebu/ebu/MemReadM
add wave -hex /testbench/dut/core/ebu/InstrReadF add wave -hex /testbench/dut/core/ebu/ebu/InstrReadF
add wave -hex /testbench/dut/core/ebu/BusState add wave -hex /testbench/dut/core/ebu/ebu/BusState
add wave -hex /testbench/dut/core/ebu/NextBusState add wave -hex /testbench/dut/core/ebu/ebu/NextBusState
add wave -hex /testbench/dut/core/ebu/HADDR add wave -hex /testbench/dut/core/ebu/ebu/HADDR
add wave -hex /testbench/dut/core/ebu/HREADY add wave -hex /testbench/dut/core/ebu/ebu/HREADY
add wave -hex /testbench/dut/core/ebu/HTRANS add wave -hex /testbench/dut/core/ebu/ebu/HTRANS
add wave -hex /testbench/dut/core/ebu/HRDATA add wave -hex /testbench/dut/core/ebu/ebu/HRDATA
add wave -hex /testbench/dut/core/ebu/HWRITE add wave -hex /testbench/dut/core/ebu/ebu/HWRITE
add wave -hex /testbench/dut/core/ebu/HWDATA add wave -hex /testbench/dut/core/ebu/ebu/HWDATA
add wave -hex /testbench/dut/core/ebu/ReadDataM add wave -hex /testbench/dut/core/ebu/ebu/ReadDataM
add wave -divider add wave -divider
add wave /testbench/dut/core/ebu/CaptureDataM add wave /testbench/dut/core/ebu/ebu/CaptureDataM
add wave /testbench/dut/core/ebu/CapturedDataAvailable add wave /testbench/dut/core/ebu/ebu/CapturedDataAvailable
add wave /testbench/dut/core/StallW add wave /testbench/dut/core/StallW
add wave -hex /testbench/dut/core/ebu/CapturedData add wave -hex /testbench/dut/core/ebu/ebu/CapturedData
add wave -hex /testbench/dut/core/ebu/ReadDataWnext add wave -hex /testbench/dut/core/ebu/ebu/ReadDataWnext
add wave -hex /testbench/dut/core/ebu/ReadDataW add wave -hex /testbench/dut/core/ebu/ebu/ReadDataW
add wave -hex /testbench/dut/core/ifu/PCW add wave -hex /testbench/dut/core/ifu/PCW
add wave -hex /testbench/dut/core/ifu/InstrW add wave -hex /testbench/dut/core/ifu/InstrW
add wave /testbench/InstrWName add wave /testbench/InstrWName
add wave /testbench/dut/core/ieu/dp/RegWriteW add wave /testbench/dut/core/ieu/dp/RegWriteW
add wave -hex /testbench/dut/core/ebu/ReadDataW add wave -hex /testbench/dut/core/ebu/ebu/ReadDataW
add wave -hex /testbench/dut/core/ieu/dp/ResultW add wave -hex /testbench/dut/core/ieu/dp/ResultW
add wave -hex /testbench/dut/core/ieu/dp/RdW add wave -hex /testbench/dut/core/ieu/dp/RdW
add wave -divider add wave -divider

2
pipelined/regression/wave-dos/default-waves.do
View File

@ -7,7 +7,7 @@ view wave
add wave /testbench/clk add wave /testbench/clk
add wave /testbench/reset add wave /testbench/reset
add wave -divider add wave -divider
#add wave /testbench/dut/core/ebu/IReadF #add wave /testbench/dut/core/ebu/ebu/IReadF
#add wave /testbench/dut/core/DataStall #add wave /testbench/dut/core/DataStall
add wave /testbench/dut/core/ICacheStallF add wave /testbench/dut/core/ICacheStallF
add wave /testbench/dut/core/StallF add wave /testbench/dut/core/StallF

94
pipelined/regression/wave-dos/linux-waves.do
View File

@ -65,53 +65,53 @@ add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/NextWalker
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/InitialWalkerState add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/InitialWalkerState
add wave -noupdate -group LSU -r /testbench/dut/core/lsu/* add wave -noupdate -group LSU -r /testbench/dut/core/lsu/*
add wave -noupdate -group DCache -r /testbench/dut/core/lsu.bus.dcache/* add wave -noupdate -group DCache -r /testbench/dut/core/lsu.bus.dcache/*
add wave -noupdate -group EBU /testbench/dut/core/ebu/clk add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/clk
add wave -noupdate -group EBU /testbench/dut/core/ebu/reset add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/reset
add wave -noupdate -group EBU /testbench/dut/core/ebu/StallW add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/StallW
add wave -noupdate -group EBU /testbench/dut/core/ebu/UnsignedLoadM add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/UnsignedLoadM
add wave -noupdate -group EBU /testbench/dut/core/ebu/AtomicMaskedM add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/AtomicMaskedM
add wave -noupdate -group EBU /testbench/dut/core/ebu/Funct7M add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/Funct7M
add wave -noupdate -group EBU /testbench/dut/core/ebu/InstrPAdrF add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/InstrPAdrF
add wave -noupdate -group EBU /testbench/dut/core/ebu/InstrReadF add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/InstrReadF
add wave -noupdate -group EBU /testbench/dut/core/ebu/InstrRData add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/InstrRData
add wave -noupdate -group EBU /testbench/dut/core/ebu/InstrAckF add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/InstrAckF
add wave -noupdate -group EBU /testbench/dut/core/ebu/DCtoAHBPAdrM add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCtoAHBPAdrM
add wave -noupdate -group EBU /testbench/dut/core/ebu/DCtoAHBReadM add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCtoAHBReadM
add wave -noupdate -group EBU /testbench/dut/core/ebu/DCtoAHBWriteM add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCtoAHBWriteM
add wave -noupdate -group EBU /testbench/dut/core/ebu/DCtoAHBWriteData add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCtoAHBWriteData
add wave -noupdate -group EBU /testbench/dut/core/ebu/DCfromAHBReadData add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCfromAHBReadData
add wave -noupdate -group EBU /testbench/dut/core/ebu/MemSizeM add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/MemSizeM
add wave -noupdate -group EBU /testbench/dut/core/ebu/DCfromAHBAck add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCfromAHBAck
add wave -noupdate -group EBU /testbench/dut/core/ebu/HRDATA add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRDATA
add wave -noupdate -group EBU /testbench/dut/core/ebu/HREADY add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HREADY
add wave -noupdate -group EBU /testbench/dut/core/ebu/HRESP add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRESP
add wave -noupdate -group EBU /testbench/dut/core/ebu/HCLK add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HCLK
add wave -noupdate -group EBU /testbench/dut/core/ebu/HRESETn add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRESETn
add wave -noupdate -group EBU /testbench/dut/core/ebu/HADDR add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HADDR
add wave -noupdate -group EBU /testbench/dut/core/ebu/HWDATA add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HWDATA
add wave -noupdate -group EBU /testbench/dut/core/ebu/HWRITE add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HWRITE
add wave -noupdate -group EBU /testbench/dut/core/ebu/HSIZE add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HSIZE
add wave -noupdate -group EBU /testbench/dut/core/ebu/HBURST add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HBURST
add wave -noupdate -group EBU /testbench/dut/core/ebu/HPROT add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HPROT
add wave -noupdate -group EBU /testbench/dut/core/ebu/HTRANS add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HTRANS
add wave -noupdate -group EBU /testbench/dut/core/ebu/HMASTLOCK add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HMASTLOCK
add wave -noupdate -group EBU /testbench/dut/core/ebu/HADDRD add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HADDRD
add wave -noupdate -group EBU /testbench/dut/core/ebu/HSIZED add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HSIZED
add wave -noupdate -group EBU /testbench/dut/core/ebu/HWRITED add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HWRITED
add wave -noupdate -group EBU /testbench/dut/core/ebu/GrantData add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/GrantData
add wave -noupdate -group EBU /testbench/dut/core/ebu/AccessAddress add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/AccessAddress
add wave -noupdate -group EBU /testbench/dut/core/ebu/ISize add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/ISize
add wave -noupdate -group EBU /testbench/dut/core/ebu/HRDATAMasked add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRDATAMasked
add wave -noupdate -group EBU /testbench/dut/core/ebu/ReadDataM add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/ReadDataM
add wave -noupdate -group EBU /testbench/dut/core/ebu/HRDATANext add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRDATANext
add wave -noupdate -group EBU /testbench/dut/core/ebu/CapturedHRDATAMasked add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/CapturedHRDATAMasked
add wave -noupdate -group EBU /testbench/dut/core/ebu/WriteData add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/WriteData
add wave -noupdate -group EBU /testbench/dut/core/ebu/IReady add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/IReady
add wave -noupdate -group EBU /testbench/dut/core/ebu/DReady add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DReady
add wave -noupdate -group EBU /testbench/dut/core/ebu/CaptureDataM add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/CaptureDataM
add wave -noupdate -group EBU /testbench/dut/core/ebu/CapturedDataAvailable add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/CapturedDataAvailable
add wave -noupdate -group EBU /testbench/dut/core/ebu/BusState add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/BusState
add wave -noupdate -group EBU /testbench/dut/core/ebu/NextBusState add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/NextBusState
add wave -noupdate -divider W add wave -noupdate -divider W
add wave -noupdate -radix hexadecimal /testbench/PCW add wave -noupdate -radix hexadecimal /testbench/PCW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidW add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidW

2
pipelined/regression/wave-dos/peripheral-waves.do
View File

@ -110,7 +110,7 @@ add wave -hex /testbench/dut/uncore/uart/uart/u/*
add wave -divider GPIO add wave -divider GPIO
add wave -hex /testbench/dut/uncore/gpio/gpio/* add wave -hex /testbench/dut/uncore/gpio/gpio/*
#add wave -divider #add wave -divider
#add wave -hex /testbench/dut/core/ebu/* #add wave -hex /testbench/dut/core/ebu/ebu/*
#add wave -divider #add wave -divider
#add wave -divider #add wave -divider

40
pipelined/regression/wave.do
View File

@ -170,26 +170,26 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/Write
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
add wave -noupdate -group AHB -color Gold /testbench/dut/core/ebu/BusState add wave -noupdate -group AHB -color Gold /testbench/dut/core/ebu/ebu/BusState
add wave -noupdate -group AHB /testbench/dut/core/ebu/NextBusState add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/NextBusState
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/AtomicMaskedM add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/ebu/AtomicMaskedM
add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/LSUBusSize add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/ebu/LSUBusSize
add wave -noupdate -group AHB /testbench/dut/core/ebu/HCLK add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HCLK
add wave -noupdate -group AHB /testbench/dut/core/ebu/HRESETn add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESETn
add wave -noupdate -group AHB /testbench/dut/core/ebu/HRDATA add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRDATA
add wave -noupdate -group AHB /testbench/dut/core/ebu/HREADY add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HREADY
add wave -noupdate -group AHB /testbench/dut/core/ebu/HRESP add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESP
add wave -noupdate -group AHB /testbench/dut/core/ebu/HADDR add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HADDR
add wave -noupdate -group AHB /testbench/dut/core/ebu/HWDATA add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWDATA
add wave -noupdate -group AHB /testbench/dut/core/ebu/HWRITE add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWRITE
add wave -noupdate -group AHB /testbench/dut/core/ebu/HSIZE add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HSIZE
add wave -noupdate -group AHB /testbench/dut/core/ebu/HBURST add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
add wave -noupdate -group AHB /testbench/dut/core/ebu/HPROT add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT
add wave -noupdate -group AHB /testbench/dut/core/ebu/HTRANS add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
add wave -noupdate -group AHB /testbench/dut/core/ebu/HMASTLOCK add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
add wave -noupdate -group AHB /testbench/dut/core/ebu/HADDRD add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HADDRD
add wave -noupdate -group AHB /testbench/dut/core/ebu/HSIZED add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HSIZED
add wave -noupdate -group AHB /testbench/dut/core/ebu/HWRITED add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWRITED
add wave -noupdate -expand -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState add wave -noupdate -expand -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/InterlockStall add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/InterlockStall

2
pipelined/src/cache/sram1p1rw.sv vendored
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@ -74,7 +74,7 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
for(index = 0; index < WIDTH/8; index++) for(index = 0; index < WIDTH/8; index++)
always_ff @(posedge clk) always_ff @(posedge clk)
if(ce & WriteEnable & ByteMask[index]) if(ce & WriteEnable & ByteMask[index])
StoredData[Adr][index*8 +: 8] <= #1 CacheWriteData[index*8 +: 8]; StoredData[Adr][index*8 +: 8] <= #1 CacheWriteData[index*8 +: 8];
assign ReadData = StoredData[AdrD]; assign ReadData = StoredData[AdrD];
end end

50
pipelined/src/generic/mem/bram1p1rw.sv
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@ -39,6 +39,7 @@ module bram1p1rw
parameter NUM_COL = 8, parameter NUM_COL = 8,
parameter COL_WIDTH = 8, parameter COL_WIDTH = 8,
parameter ADDR_WIDTH = 10, parameter ADDR_WIDTH = 10,
parameter PRELOAD_ENABLED = 0,
// Addr Width in bits : 2 *ADDR_WIDTH = RAM Depth // Addr Width in bits : 2 *ADDR_WIDTH = RAM Depth
parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits
//---------------------------------------------------------------------- //----------------------------------------------------------------------
@ -54,6 +55,55 @@ module bram1p1rw
logic [DATA_WIDTH-1:0] RAM [(2**ADDR_WIDTH)-1:0]; logic [DATA_WIDTH-1:0] RAM [(2**ADDR_WIDTH)-1:0];
integer i; integer i;
if(PRELOAD_ENABLED) begin
initial begin
RAM[0] = 64'h9581819300002197;
RAM[1] = 64'h4281420141014081;
RAM[2] = 64'h4481440143814301;
RAM[3] = 64'h4681460145814501;
RAM[4] = 64'h4881480147814701;
RAM[5] = 64'h4a814a0149814901;
RAM[6] = 64'h4c814c014b814b01;
RAM[7] = 64'h4e814e014d814d01;
RAM[8] = 64'h0110011b4f814f01;
RAM[9] = 64'h059b45011161016e;
RAM[10] = 64'h0004063705fe0010;
RAM[11] = 64'h05a000ef8006061b;
RAM[12] = 64'h0ff003930000100f;
RAM[13] = 64'h4e952e3110060e37;
RAM[14] = 64'hc602829b0053f2b7;
RAM[15] = 64'h2023fe02dfe312fd;
RAM[16] = 64'h829b0053f2b7007e;
RAM[17] = 64'hfe02dfe312fdc602;
RAM[18] = 64'h4de31efd000e2023;
RAM[19] = 64'h059bf1402573fdd0;
RAM[20] = 64'h0000061705e20870;
RAM[21] = 64'h0010029b01260613;
RAM[22] = 64'h11010002806702fe;
RAM[23] = 64'h84b2842ae426e822;
RAM[24] = 64'h892ee04aec064511;
RAM[25] = 64'h06e000ef07e000ef;
RAM[26] = 64'h979334fd02905563;
RAM[27] = 64'h07930177d4930204;
RAM[28] = 64'h4089093394be2004;
RAM[29] = 64'h04138522008905b3;
RAM[30] = 64'h19e3014000ef2004;
RAM[31] = 64'h64a2644260e2fe94;
RAM[32] = 64'h6749808261056902;
RAM[33] = 64'hdfed8b8510472783;
RAM[34] = 64'h2423479110a73823;
RAM[35] = 64'h10472783674910f7;
RAM[36] = 64'h20058693ffed8b89;
RAM[37] = 64'h05a1118737836749;
RAM[38] = 64'hfed59be3fef5bc23;
RAM[39] = 64'h1047278367498082;
RAM[40] = 64'h47858082dfed8b85;
RAM[41] = 64'h40a7853b4015551b;
RAM[42] = 64'h808210a7a02367c9;
end
end
always @ (posedge clk) begin always @ (posedge clk) begin
dout <= RAM[addr]; dout <= RAM[addr];
if(we) begin if(we) begin

2
pipelined/src/uncore/ram_ahb.sv
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@ -70,7 +70,7 @@ module ram_ahb #(parameter BASE=0, RANGE = 65535) (
mux2 #(32) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr); mux2 #(32) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr);
// single-ported RAM // single-ported RAM
bram1p1rw #(`XLEN/8, 8, ADDR_WIDTH) bram1p1rw #(`XLEN/8, 8, ADDR_WIDTH, `FPGA)
memory(.clk(HCLK), .we(memwriteD), .bwe(HWSTRB), .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRam), .din(HWDATA)); memory(.clk(HCLK), .we(memwriteD), .bwe(HWSTRB), .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRam), .din(HWDATA));
endmodule endmodule

4
pipelined/src/wally/wallypipelinedcore.sv
View File

@ -292,7 +292,8 @@ module wallypipelinedcore (
// *** Ross: please make EBU conditional when only supporting internal memories // *** Ross: please make EBU conditional when only supporting internal memories
ahblite ebu(// IFU connections if(`DBUS | `IBUS) begin : ebu
ahblite ebu(// IFU connections
.clk, .reset, .clk, .reset,
.UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00), .UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00),
.IFUBusAdr, .IFUBusRead, .IFUBusAdr, .IFUBusRead,
@ -316,6 +317,7 @@ module wallypipelinedcore (
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
.HPROT, .HTRANS, .HMASTLOCK, .HADDRD, .HSIZED, .HPROT, .HTRANS, .HMASTLOCK, .HADDRD, .HSIZED,
.HWRITED); .HWRITED);
end
hazard hzu( hazard hzu(