From 7ecd1c7d5f49c7375c5e76bde03a34ea3f1b0bbd Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Thu, 30 May 2024 15:48:27 -0500 Subject: [PATCH 1/2] The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file. --- fpga/constraints/debug6.xdc | 549 ++++++++++++ fpga/constraints/marked_debug_all.txt | 1 + fpga/generator/wally.tcl | 4 +- fpga/renumber.py | 33 + fpga/src/fpgaTop.sv | 1130 +++++++++++++++++++++++++ 5 files changed, 1715 insertions(+), 2 deletions(-) create mode 100644 fpga/constraints/debug6.xdc create mode 100755 fpga/renumber.py create mode 100644 fpga/src/fpgaTop.sv diff --git a/fpga/constraints/debug6.xdc b/fpga/constraints/debug6.xdc new file mode 100644 index 000000000..88ae08ef8 --- /dev/null +++ b/fpga/constraints/debug6.xdc @@ -0,0 +1,549 @@ +create_debug_core u_ila_0 ila + +set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] +set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] +set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] +set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] +startgroup +set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ] +set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ] +set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ] +endgroup +connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]] +set_property port_width 64 [get_debug_ports u_ila_0/probe0] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]] +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe1] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list {wallypipelinedsoc/core/HRDATA[0]} {wallypipelinedsoc/core/HRDATA[1]} {wallypipelinedsoc/core/HRDATA[2]} {wallypipelinedsoc/core/HRDATA[3]} {wallypipelinedsoc/core/HRDATA[4]} {wallypipelinedsoc/core/HRDATA[5]} {wallypipelinedsoc/core/HRDATA[6]} {wallypipelinedsoc/core/HRDATA[7]} {wallypipelinedsoc/core/HRDATA[8]} {wallypipelinedsoc/core/HRDATA[9]} {wallypipelinedsoc/core/HRDATA[10]} {wallypipelinedsoc/core/HRDATA[11]} {wallypipelinedsoc/core/HRDATA[12]} {wallypipelinedsoc/core/HRDATA[13]} {wallypipelinedsoc/core/HRDATA[14]} {wallypipelinedsoc/core/HRDATA[15]} {wallypipelinedsoc/core/HRDATA[16]} {wallypipelinedsoc/core/HRDATA[17]} {wallypipelinedsoc/core/HRDATA[18]} {wallypipelinedsoc/core/HRDATA[19]} {wallypipelinedsoc/core/HRDATA[20]} {wallypipelinedsoc/core/HRDATA[21]} {wallypipelinedsoc/core/HRDATA[22]} {wallypipelinedsoc/core/HRDATA[23]} {wallypipelinedsoc/core/HRDATA[24]} {wallypipelinedsoc/core/HRDATA[25]} {wallypipelinedsoc/core/HRDATA[26]} {wallypipelinedsoc/core/HRDATA[27]} {wallypipelinedsoc/core/HRDATA[28]} {wallypipelinedsoc/core/HRDATA[29]} {wallypipelinedsoc/core/HRDATA[30]} {wallypipelinedsoc/core/HRDATA[31]} {wallypipelinedsoc/core/HRDATA[32]} {wallypipelinedsoc/core/HRDATA[33]} {wallypipelinedsoc/core/HRDATA[34]} {wallypipelinedsoc/core/HRDATA[35]} {wallypipelinedsoc/core/HRDATA[36]} {wallypipelinedsoc/core/HRDATA[37]} {wallypipelinedsoc/core/HRDATA[38]} {wallypipelinedsoc/core/HRDATA[39]} {wallypipelinedsoc/core/HRDATA[40]} {wallypipelinedsoc/core/HRDATA[41]} {wallypipelinedsoc/core/HRDATA[42]} {wallypipelinedsoc/core/HRDATA[43]} {wallypipelinedsoc/core/HRDATA[44]} {wallypipelinedsoc/core/HRDATA[45]} {wallypipelinedsoc/core/HRDATA[46]} {wallypipelinedsoc/core/HRDATA[47]} {wallypipelinedsoc/core/HRDATA[48]} {wallypipelinedsoc/core/HRDATA[49]} {wallypipelinedsoc/core/HRDATA[50]} {wallypipelinedsoc/core/HRDATA[51]} {wallypipelinedsoc/core/HRDATA[52]} {wallypipelinedsoc/core/HRDATA[53]} {wallypipelinedsoc/core/HRDATA[54]} {wallypipelinedsoc/core/HRDATA[55]} {wallypipelinedsoc/core/HRDATA[56]} {wallypipelinedsoc/core/HRDATA[57]} {wallypipelinedsoc/core/HRDATA[58]} {wallypipelinedsoc/core/HRDATA[59]} {wallypipelinedsoc/core/HRDATA[60]} {wallypipelinedsoc/core/HRDATA[61]} {wallypipelinedsoc/core/HRDATA[62]} {wallypipelinedsoc/core/HRDATA[63]} ]] +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe2] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHADDR[0]} {wallypipelinedsoc/core/lsu/LSUHADDR[1]} {wallypipelinedsoc/core/lsu/LSUHADDR[2]} {wallypipelinedsoc/core/lsu/LSUHADDR[3]} {wallypipelinedsoc/core/lsu/LSUHADDR[4]} {wallypipelinedsoc/core/lsu/LSUHADDR[5]} {wallypipelinedsoc/core/lsu/LSUHADDR[6]} {wallypipelinedsoc/core/lsu/LSUHADDR[7]} {wallypipelinedsoc/core/lsu/LSUHADDR[8]} {wallypipelinedsoc/core/lsu/LSUHADDR[9]} {wallypipelinedsoc/core/lsu/LSUHADDR[10]} {wallypipelinedsoc/core/lsu/LSUHADDR[11]} {wallypipelinedsoc/core/lsu/LSUHADDR[12]} {wallypipelinedsoc/core/lsu/LSUHADDR[13]} {wallypipelinedsoc/core/lsu/LSUHADDR[14]} {wallypipelinedsoc/core/lsu/LSUHADDR[15]} {wallypipelinedsoc/core/lsu/LSUHADDR[16]} {wallypipelinedsoc/core/lsu/LSUHADDR[17]} {wallypipelinedsoc/core/lsu/LSUHADDR[18]} {wallypipelinedsoc/core/lsu/LSUHADDR[19]} {wallypipelinedsoc/core/lsu/LSUHADDR[20]} {wallypipelinedsoc/core/lsu/LSUHADDR[21]} {wallypipelinedsoc/core/lsu/LSUHADDR[22]} {wallypipelinedsoc/core/lsu/LSUHADDR[23]} {wallypipelinedsoc/core/lsu/LSUHADDR[24]} {wallypipelinedsoc/core/lsu/LSUHADDR[25]} {wallypipelinedsoc/core/lsu/LSUHADDR[26]} {wallypipelinedsoc/core/lsu/LSUHADDR[27]} {wallypipelinedsoc/core/lsu/LSUHADDR[28]} {wallypipelinedsoc/core/lsu/LSUHADDR[29]} {wallypipelinedsoc/core/lsu/LSUHADDR[30]} {wallypipelinedsoc/core/lsu/LSUHADDR[31]} ]] +create_debug_port u_ila_0 probe +set_property port_width 6 [get_debug_ports u_ila_0/probe3] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/MIP_REGW[11]} ]] +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe4] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MCAUSE_REGW[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe5] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/core/lsu/ReadDataM[0]} {wallypipelinedsoc/core/lsu/ReadDataM[1]} {wallypipelinedsoc/core/lsu/ReadDataM[2]} {wallypipelinedsoc/core/lsu/ReadDataM[3]} {wallypipelinedsoc/core/lsu/ReadDataM[4]} {wallypipelinedsoc/core/lsu/ReadDataM[5]} {wallypipelinedsoc/core/lsu/ReadDataM[6]} {wallypipelinedsoc/core/lsu/ReadDataM[7]} {wallypipelinedsoc/core/lsu/ReadDataM[8]} {wallypipelinedsoc/core/lsu/ReadDataM[9]} {wallypipelinedsoc/core/lsu/ReadDataM[10]} {wallypipelinedsoc/core/lsu/ReadDataM[11]} {wallypipelinedsoc/core/lsu/ReadDataM[12]} {wallypipelinedsoc/core/lsu/ReadDataM[13]} {wallypipelinedsoc/core/lsu/ReadDataM[14]} {wallypipelinedsoc/core/lsu/ReadDataM[15]} {wallypipelinedsoc/core/lsu/ReadDataM[16]} {wallypipelinedsoc/core/lsu/ReadDataM[17]} {wallypipelinedsoc/core/lsu/ReadDataM[18]} {wallypipelinedsoc/core/lsu/ReadDataM[19]} {wallypipelinedsoc/core/lsu/ReadDataM[20]} {wallypipelinedsoc/core/lsu/ReadDataM[21]} {wallypipelinedsoc/core/lsu/ReadDataM[22]} {wallypipelinedsoc/core/lsu/ReadDataM[23]} {wallypipelinedsoc/core/lsu/ReadDataM[24]} {wallypipelinedsoc/core/lsu/ReadDataM[25]} {wallypipelinedsoc/core/lsu/ReadDataM[26]} {wallypipelinedsoc/core/lsu/ReadDataM[27]} {wallypipelinedsoc/core/lsu/ReadDataM[28]} {wallypipelinedsoc/core/lsu/ReadDataM[29]} {wallypipelinedsoc/core/lsu/ReadDataM[30]} {wallypipelinedsoc/core/lsu/ReadDataM[31]} {wallypipelinedsoc/core/lsu/ReadDataM[32]} {wallypipelinedsoc/core/lsu/ReadDataM[33]} {wallypipelinedsoc/core/lsu/ReadDataM[34]} {wallypipelinedsoc/core/lsu/ReadDataM[35]} {wallypipelinedsoc/core/lsu/ReadDataM[36]} {wallypipelinedsoc/core/lsu/ReadDataM[37]} {wallypipelinedsoc/core/lsu/ReadDataM[38]} {wallypipelinedsoc/core/lsu/ReadDataM[39]} {wallypipelinedsoc/core/lsu/ReadDataM[40]} {wallypipelinedsoc/core/lsu/ReadDataM[41]} {wallypipelinedsoc/core/lsu/ReadDataM[42]} {wallypipelinedsoc/core/lsu/ReadDataM[43]} {wallypipelinedsoc/core/lsu/ReadDataM[44]} {wallypipelinedsoc/core/lsu/ReadDataM[45]} {wallypipelinedsoc/core/lsu/ReadDataM[46]} {wallypipelinedsoc/core/lsu/ReadDataM[47]} {wallypipelinedsoc/core/lsu/ReadDataM[48]} {wallypipelinedsoc/core/lsu/ReadDataM[49]} {wallypipelinedsoc/core/lsu/ReadDataM[50]} {wallypipelinedsoc/core/lsu/ReadDataM[51]} {wallypipelinedsoc/core/lsu/ReadDataM[52]} {wallypipelinedsoc/core/lsu/ReadDataM[53]} {wallypipelinedsoc/core/lsu/ReadDataM[54]} {wallypipelinedsoc/core/lsu/ReadDataM[55]} {wallypipelinedsoc/core/lsu/ReadDataM[56]} {wallypipelinedsoc/core/lsu/ReadDataM[57]} {wallypipelinedsoc/core/lsu/ReadDataM[58]} {wallypipelinedsoc/core/lsu/ReadDataM[59]} {wallypipelinedsoc/core/lsu/ReadDataM[60]} {wallypipelinedsoc/core/lsu/ReadDataM[61]} {wallypipelinedsoc/core/lsu/ReadDataM[62]} {wallypipelinedsoc/core/lsu/ReadDataM[63]} ]] +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe6] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/core/lsu/WriteDataM[0]} {wallypipelinedsoc/core/lsu/WriteDataM[1]} {wallypipelinedsoc/core/lsu/WriteDataM[2]} {wallypipelinedsoc/core/lsu/WriteDataM[3]} {wallypipelinedsoc/core/lsu/WriteDataM[4]} {wallypipelinedsoc/core/lsu/WriteDataM[5]} {wallypipelinedsoc/core/lsu/WriteDataM[6]} {wallypipelinedsoc/core/lsu/WriteDataM[7]} {wallypipelinedsoc/core/lsu/WriteDataM[8]} {wallypipelinedsoc/core/lsu/WriteDataM[9]} {wallypipelinedsoc/core/lsu/WriteDataM[10]} {wallypipelinedsoc/core/lsu/WriteDataM[11]} {wallypipelinedsoc/core/lsu/WriteDataM[12]} {wallypipelinedsoc/core/lsu/WriteDataM[13]} {wallypipelinedsoc/core/lsu/WriteDataM[14]} {wallypipelinedsoc/core/lsu/WriteDataM[15]} {wallypipelinedsoc/core/lsu/WriteDataM[16]} {wallypipelinedsoc/core/lsu/WriteDataM[17]} {wallypipelinedsoc/core/lsu/WriteDataM[18]} {wallypipelinedsoc/core/lsu/WriteDataM[19]} {wallypipelinedsoc/core/lsu/WriteDataM[20]} {wallypipelinedsoc/core/lsu/WriteDataM[21]} {wallypipelinedsoc/core/lsu/WriteDataM[22]} {wallypipelinedsoc/core/lsu/WriteDataM[23]} {wallypipelinedsoc/core/lsu/WriteDataM[24]} {wallypipelinedsoc/core/lsu/WriteDataM[25]} {wallypipelinedsoc/core/lsu/WriteDataM[26]} {wallypipelinedsoc/core/lsu/WriteDataM[27]} {wallypipelinedsoc/core/lsu/WriteDataM[28]} {wallypipelinedsoc/core/lsu/WriteDataM[29]} {wallypipelinedsoc/core/lsu/WriteDataM[30]} {wallypipelinedsoc/core/lsu/WriteDataM[31]} {wallypipelinedsoc/core/lsu/WriteDataM[32]} {wallypipelinedsoc/core/lsu/WriteDataM[33]} {wallypipelinedsoc/core/lsu/WriteDataM[34]} {wallypipelinedsoc/core/lsu/WriteDataM[35]} {wallypipelinedsoc/core/lsu/WriteDataM[36]} {wallypipelinedsoc/core/lsu/WriteDataM[37]} {wallypipelinedsoc/core/lsu/WriteDataM[38]} {wallypipelinedsoc/core/lsu/WriteDataM[39]} {wallypipelinedsoc/core/lsu/WriteDataM[40]} {wallypipelinedsoc/core/lsu/WriteDataM[41]} {wallypipelinedsoc/core/lsu/WriteDataM[42]} {wallypipelinedsoc/core/lsu/WriteDataM[43]} {wallypipelinedsoc/core/lsu/WriteDataM[44]} {wallypipelinedsoc/core/lsu/WriteDataM[45]} {wallypipelinedsoc/core/lsu/WriteDataM[46]} {wallypipelinedsoc/core/lsu/WriteDataM[47]} {wallypipelinedsoc/core/lsu/WriteDataM[48]} {wallypipelinedsoc/core/lsu/WriteDataM[49]} {wallypipelinedsoc/core/lsu/WriteDataM[50]} {wallypipelinedsoc/core/lsu/WriteDataM[51]} {wallypipelinedsoc/core/lsu/WriteDataM[52]} {wallypipelinedsoc/core/lsu/WriteDataM[53]} {wallypipelinedsoc/core/lsu/WriteDataM[54]} {wallypipelinedsoc/core/lsu/WriteDataM[55]} {wallypipelinedsoc/core/lsu/WriteDataM[56]} {wallypipelinedsoc/core/lsu/WriteDataM[57]} {wallypipelinedsoc/core/lsu/WriteDataM[58]} {wallypipelinedsoc/core/lsu/WriteDataM[59]} {wallypipelinedsoc/core/lsu/WriteDataM[60]} {wallypipelinedsoc/core/lsu/WriteDataM[61]} {wallypipelinedsoc/core/lsu/WriteDataM[62]} {wallypipelinedsoc/core/lsu/WriteDataM[63]} ]] +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe7] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] +connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/core/PCM[0]} {wallypipelinedsoc/core/PCM[1]} {wallypipelinedsoc/core/PCM[2]} {wallypipelinedsoc/core/PCM[3]} {wallypipelinedsoc/core/PCM[4]} {wallypipelinedsoc/core/PCM[5]} {wallypipelinedsoc/core/PCM[6]} {wallypipelinedsoc/core/PCM[7]} {wallypipelinedsoc/core/PCM[8]} {wallypipelinedsoc/core/PCM[9]} {wallypipelinedsoc/core/PCM[10]} {wallypipelinedsoc/core/PCM[11]} {wallypipelinedsoc/core/PCM[12]} {wallypipelinedsoc/core/PCM[13]} {wallypipelinedsoc/core/PCM[14]} {wallypipelinedsoc/core/PCM[15]} {wallypipelinedsoc/core/PCM[16]} {wallypipelinedsoc/core/PCM[17]} {wallypipelinedsoc/core/PCM[18]} {wallypipelinedsoc/core/PCM[19]} {wallypipelinedsoc/core/PCM[20]} {wallypipelinedsoc/core/PCM[21]} {wallypipelinedsoc/core/PCM[22]} {wallypipelinedsoc/core/PCM[23]} {wallypipelinedsoc/core/PCM[24]} {wallypipelinedsoc/core/PCM[25]} {wallypipelinedsoc/core/PCM[26]} {wallypipelinedsoc/core/PCM[27]} {wallypipelinedsoc/core/PCM[28]} {wallypipelinedsoc/core/PCM[29]} {wallypipelinedsoc/core/PCM[30]} {wallypipelinedsoc/core/PCM[31]} {wallypipelinedsoc/core/PCM[32]} {wallypipelinedsoc/core/PCM[33]} {wallypipelinedsoc/core/PCM[34]} {wallypipelinedsoc/core/PCM[35]} {wallypipelinedsoc/core/PCM[36]} {wallypipelinedsoc/core/PCM[37]} {wallypipelinedsoc/core/PCM[38]} {wallypipelinedsoc/core/PCM[39]} {wallypipelinedsoc/core/PCM[40]} {wallypipelinedsoc/core/PCM[41]} {wallypipelinedsoc/core/PCM[42]} {wallypipelinedsoc/core/PCM[43]} {wallypipelinedsoc/core/PCM[44]} {wallypipelinedsoc/core/PCM[45]} {wallypipelinedsoc/core/PCM[46]} {wallypipelinedsoc/core/PCM[47]} {wallypipelinedsoc/core/PCM[48]} {wallypipelinedsoc/core/PCM[49]} {wallypipelinedsoc/core/PCM[50]} {wallypipelinedsoc/core/PCM[51]} {wallypipelinedsoc/core/PCM[52]} {wallypipelinedsoc/core/PCM[53]} {wallypipelinedsoc/core/PCM[54]} {wallypipelinedsoc/core/PCM[55]} {wallypipelinedsoc/core/PCM[56]} {wallypipelinedsoc/core/PCM[57]} {wallypipelinedsoc/core/PCM[58]} {wallypipelinedsoc/core/PCM[59]} {wallypipelinedsoc/core/PCM[60]} {wallypipelinedsoc/core/PCM[61]} {wallypipelinedsoc/core/PCM[62]} {wallypipelinedsoc/core/PCM[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe8] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] +connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/core/IEUAdrM[0]} {wallypipelinedsoc/core/IEUAdrM[1]} {wallypipelinedsoc/core/IEUAdrM[2]} {wallypipelinedsoc/core/IEUAdrM[3]} {wallypipelinedsoc/core/IEUAdrM[4]} {wallypipelinedsoc/core/IEUAdrM[5]} {wallypipelinedsoc/core/IEUAdrM[6]} {wallypipelinedsoc/core/IEUAdrM[7]} {wallypipelinedsoc/core/IEUAdrM[8]} {wallypipelinedsoc/core/IEUAdrM[9]} {wallypipelinedsoc/core/IEUAdrM[10]} {wallypipelinedsoc/core/IEUAdrM[11]} {wallypipelinedsoc/core/IEUAdrM[12]} {wallypipelinedsoc/core/IEUAdrM[13]} {wallypipelinedsoc/core/IEUAdrM[14]} {wallypipelinedsoc/core/IEUAdrM[15]} {wallypipelinedsoc/core/IEUAdrM[16]} {wallypipelinedsoc/core/IEUAdrM[17]} {wallypipelinedsoc/core/IEUAdrM[18]} {wallypipelinedsoc/core/IEUAdrM[19]} {wallypipelinedsoc/core/IEUAdrM[20]} {wallypipelinedsoc/core/IEUAdrM[21]} {wallypipelinedsoc/core/IEUAdrM[22]} {wallypipelinedsoc/core/IEUAdrM[23]} {wallypipelinedsoc/core/IEUAdrM[24]} {wallypipelinedsoc/core/IEUAdrM[25]} {wallypipelinedsoc/core/IEUAdrM[26]} {wallypipelinedsoc/core/IEUAdrM[27]} {wallypipelinedsoc/core/IEUAdrM[28]} {wallypipelinedsoc/core/IEUAdrM[29]} {wallypipelinedsoc/core/IEUAdrM[30]} {wallypipelinedsoc/core/IEUAdrM[31]} {wallypipelinedsoc/core/IEUAdrM[32]} {wallypipelinedsoc/core/IEUAdrM[33]} {wallypipelinedsoc/core/IEUAdrM[34]} {wallypipelinedsoc/core/IEUAdrM[35]} {wallypipelinedsoc/core/IEUAdrM[36]} {wallypipelinedsoc/core/IEUAdrM[37]} {wallypipelinedsoc/core/IEUAdrM[38]} {wallypipelinedsoc/core/IEUAdrM[39]} {wallypipelinedsoc/core/IEUAdrM[40]} {wallypipelinedsoc/core/IEUAdrM[41]} {wallypipelinedsoc/core/IEUAdrM[42]} {wallypipelinedsoc/core/IEUAdrM[43]} {wallypipelinedsoc/core/IEUAdrM[44]} {wallypipelinedsoc/core/IEUAdrM[45]} {wallypipelinedsoc/core/IEUAdrM[46]} {wallypipelinedsoc/core/IEUAdrM[47]} {wallypipelinedsoc/core/IEUAdrM[48]} {wallypipelinedsoc/core/IEUAdrM[49]} {wallypipelinedsoc/core/IEUAdrM[50]} {wallypipelinedsoc/core/IEUAdrM[51]} {wallypipelinedsoc/core/IEUAdrM[52]} {wallypipelinedsoc/core/IEUAdrM[53]} {wallypipelinedsoc/core/IEUAdrM[54]} {wallypipelinedsoc/core/IEUAdrM[55]} {wallypipelinedsoc/core/IEUAdrM[56]} {wallypipelinedsoc/core/IEUAdrM[57]} {wallypipelinedsoc/core/IEUAdrM[58]} {wallypipelinedsoc/core/IEUAdrM[59]} {wallypipelinedsoc/core/IEUAdrM[60]} {wallypipelinedsoc/core/IEUAdrM[61]} {wallypipelinedsoc/core/IEUAdrM[62]} {wallypipelinedsoc/core/IEUAdrM[63]} ]] +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe9] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] +connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/core/InstrM[0]} {wallypipelinedsoc/core/InstrM[1]} {wallypipelinedsoc/core/InstrM[2]} {wallypipelinedsoc/core/InstrM[3]} {wallypipelinedsoc/core/InstrM[4]} {wallypipelinedsoc/core/InstrM[5]} {wallypipelinedsoc/core/InstrM[6]} {wallypipelinedsoc/core/InstrM[7]} {wallypipelinedsoc/core/InstrM[8]} {wallypipelinedsoc/core/InstrM[9]} {wallypipelinedsoc/core/InstrM[10]} {wallypipelinedsoc/core/InstrM[11]} {wallypipelinedsoc/core/InstrM[12]} {wallypipelinedsoc/core/InstrM[13]} {wallypipelinedsoc/core/InstrM[14]} {wallypipelinedsoc/core/InstrM[15]} {wallypipelinedsoc/core/InstrM[16]} {wallypipelinedsoc/core/InstrM[17]} {wallypipelinedsoc/core/InstrM[18]} {wallypipelinedsoc/core/InstrM[19]} {wallypipelinedsoc/core/InstrM[20]} {wallypipelinedsoc/core/InstrM[21]} {wallypipelinedsoc/core/InstrM[22]} {wallypipelinedsoc/core/InstrM[23]} {wallypipelinedsoc/core/InstrM[24]} {wallypipelinedsoc/core/InstrM[25]} {wallypipelinedsoc/core/InstrM[26]} {wallypipelinedsoc/core/InstrM[27]} {wallypipelinedsoc/core/InstrM[28]} {wallypipelinedsoc/core/InstrM[29]} {wallypipelinedsoc/core/InstrM[30]} {wallypipelinedsoc/core/InstrM[31]} ]] +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe10] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] +connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/core/MemRWM[0]} {wallypipelinedsoc/core/MemRWM[1]} ]] +create_debug_port u_ila_0 probe +set_property port_width 6 [get_debug_ports u_ila_0/probe11] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] +connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[11]} ]] +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe12] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] +connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEPC_REGW[63]} ]] +create_debug_port u_ila_0 probe +set_property port_width 6 [get_debug_ports u_ila_0/probe13] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] +connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[11]} ]] + + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe14] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] +connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[0]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[1]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[2]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe15] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] +connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SEPC_REGW[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe16] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] +connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SCAUSE_REGW[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe17] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] +connect_debug_port u_ila_0/probe17 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{wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]] + + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe18] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] +connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/STVEC_REGW[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 6 [get_debug_ports u_ila_0/probe19] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] +connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[11]} ]] + + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe20] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] +connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHSIZE[0]} {wallypipelinedsoc/core/lsu/LSUHSIZE[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe21] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] +connect_debug_port u_ila_0/probe21 [get_nets [list wallypipelinedsoc/core/lsu/LSUHREADY ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe22] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] +connect_debug_port u_ila_0/probe22 [get_nets [list wallypipelinedsoc/core/lsu/LSUHWRITE ]] + +create_debug_port u_ila_0 probe +set_property port_width 3 [get_debug_ports u_ila_0/probe23] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] +connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHBURST[0]} wallypipelinedsoc/core/lsu/LSUHBURST[1] wallypipelinedsoc/core/lsu/LSUHBURST[2] ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe24] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] +connect_debug_port u_ila_0/probe24 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/BreakpointFaultM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe25] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] +connect_debug_port u_ila_0/probe25 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/EcallFaultM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe26] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] +connect_debug_port u_ila_0/probe26 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/IllegalInstrFaultM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe27] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27] +connect_debug_port u_ila_0/probe27 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/InstrAccessFaultM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe28] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28] +connect_debug_port u_ila_0/probe28 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/InstrPageFaultM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe29] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29] +connect_debug_port u_ila_0/probe29 [get_nets [list wallypipelinedsoc/core/InstrValidM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe30] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30] +connect_debug_port u_ila_0/probe30 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadAccessFaultM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe31] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31] +connect_debug_port u_ila_0/probe31 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadMisalignedFaultM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe32] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32] +connect_debug_port u_ila_0/probe32 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/LoadPageFaultM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe33] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33] +connect_debug_port u_ila_0/probe33 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoAccessFaultM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe34] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34] +connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoMisalignedFaultM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe35] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35] +connect_debug_port u_ila_0/probe35 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe36] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36] +connect_debug_port u_ila_0/probe36 [get_nets [list wallypipelinedsoc/core/TrapM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe37] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37] +connect_debug_port u_ila_0/probe37 [get_nets [list wallypipelinedsoc/core/hzu/BPWrongE ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe38] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38] +connect_debug_port u_ila_0/probe38 [get_nets [list wallypipelinedsoc/core/hzu/CSRWriteFenceM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe39] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39] +connect_debug_port u_ila_0/probe39 [get_nets [list wallypipelinedsoc/core/hzu/RetM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe40] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40] +connect_debug_port u_ila_0/probe40 [get_nets [list wallypipelinedsoc/core/TrapM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe41] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41] +connect_debug_port u_ila_0/probe41 [get_nets [list wallypipelinedsoc/core/hzu/LSUStallM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe42] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42] +connect_debug_port u_ila_0/probe42 [get_nets [list wallypipelinedsoc/core/hzu/IFUStallF ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe43] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43] +connect_debug_port u_ila_0/probe43 [get_nets [list wallypipelinedsoc/core/hzu/FPUStallD ]] + +create_debug_port u_ila_0 probe +set_property port_width 7 [get_debug_ports u_ila_0/probe44] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44] +connect_debug_port u_ila_0/probe44 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[0][1]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[0][2]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[0][3]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[0][4]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[0][5]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[0][6]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[0][7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe45] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45] +connect_debug_port u_ila_0/probe45 [get_nets [list wallypipelinedsoc/core/hzu/FDivBusyE ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe46] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46] +connect_debug_port u_ila_0/probe46 [get_nets [list wallypipelinedsoc/core/hzu/StallF ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe47] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47] +connect_debug_port u_ila_0/probe47 [get_nets [list wallypipelinedsoc/core/hzu/StallDCause]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe48] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48] +connect_debug_port u_ila_0/probe48 [get_nets [list wallypipelinedsoc/core/hzu/StallE ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe49] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49] +connect_debug_port u_ila_0/probe49 [get_nets [list wallypipelinedsoc/core/hzu/StallM ]] + +# StallW is StallM. trying to connect to StallW causes issues. +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe50] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50] +connect_debug_port u_ila_0/probe50 [get_nets [list wallypipelinedsoc/core/hzu/StallM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe51] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51] +connect_debug_port u_ila_0/probe51 [get_nets [list wallypipelinedsoc/core/hzu/FlushD ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe52] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52] +connect_debug_port u_ila_0/probe52 [get_nets [list wallypipelinedsoc/core/hzu/FlushE ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe53] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53] +connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsoc/core/hzu/FlushM ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe54] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54] +connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/core/hzu/FlushW ]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe55] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55] +connect_debug_port u_ila_0/probe55 [get_nets [list {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[0]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[1]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[2]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3]}]] + + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe56] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56] +connect_debug_port u_ila_0/probe56 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe57] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57] +connect_debug_port u_ila_0/probe57 [get_nets [list wallypipelinedsoc/core/ifu/IFUHREADY ]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe58] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58] +connect_debug_port u_ila_0/probe58 [get_nets [list {wallypipelinedsoc/core/ifu/IFUHADDR[0]} {wallypipelinedsoc/core/ifu/IFUHADDR[1]} {wallypipelinedsoc/core/ifu/IFUHADDR[2]} {wallypipelinedsoc/core/ifu/IFUHADDR[3]} {wallypipelinedsoc/core/ifu/IFUHADDR[4]} {wallypipelinedsoc/core/ifu/IFUHADDR[5]} {wallypipelinedsoc/core/ifu/IFUHADDR[6]} {wallypipelinedsoc/core/ifu/IFUHADDR[7]} {wallypipelinedsoc/core/ifu/IFUHADDR[8]} {wallypipelinedsoc/core/ifu/IFUHADDR[9]} {wallypipelinedsoc/core/ifu/IFUHADDR[10]} {wallypipelinedsoc/core/ifu/IFUHADDR[11]} {wallypipelinedsoc/core/ifu/IFUHADDR[12]} {wallypipelinedsoc/core/ifu/IFUHADDR[13]} {wallypipelinedsoc/core/ifu/IFUHADDR[14]} {wallypipelinedsoc/core/ifu/IFUHADDR[15]} {wallypipelinedsoc/core/ifu/IFUHADDR[16]} {wallypipelinedsoc/core/ifu/IFUHADDR[17]} {wallypipelinedsoc/core/ifu/IFUHADDR[18]} {wallypipelinedsoc/core/ifu/IFUHADDR[19]} {wallypipelinedsoc/core/ifu/IFUHADDR[20]} {wallypipelinedsoc/core/ifu/IFUHADDR[21]} {wallypipelinedsoc/core/ifu/IFUHADDR[22]} {wallypipelinedsoc/core/ifu/IFUHADDR[23]} {wallypipelinedsoc/core/ifu/IFUHADDR[24]} {wallypipelinedsoc/core/ifu/IFUHADDR[25]} {wallypipelinedsoc/core/ifu/IFUHADDR[26]} {wallypipelinedsoc/core/ifu/IFUHADDR[27]} {wallypipelinedsoc/core/ifu/IFUHADDR[28]} {wallypipelinedsoc/core/ifu/IFUHADDR[29]} {wallypipelinedsoc/core/ifu/IFUHADDR[30]} {wallypipelinedsoc/core/ifu/IFUHADDR[31]}]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe59] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59] +connect_debug_port u_ila_0/probe59 [get_nets [list {wallypipelinedsoc/core/ifu/IFUHTRANS[0]} {wallypipelinedsoc/core/ifu/IFUHTRANS[0]}]] + + + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe60] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60] +connect_debug_port u_ila_0/probe60 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HTRANS[0]} {wallypipelinedsoc/core/ebu.ebu/HTRANS[1]}]] + +create_debug_port u_ila_0 probe +set_property port_width 53 [get_debug_ports u_ila_0/probe61] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61] +connect_debug_port u_ila_0/probe61 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][1]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][2]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][3]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][4]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][5]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][6]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][7]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][8]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][9]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][10]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][11]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][12]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][13]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][14]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][15]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][16]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][17]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][18]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][19]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][20]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][21]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][22]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][23]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][24]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][25]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][26]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][27]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][28]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][29]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][30]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][31]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][32]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][33]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][34]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][35]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][36]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][37]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][38]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][39]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][40]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][41]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][42]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][43]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][44]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][45]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][46]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][47]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][48]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][49]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][50]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][51]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][52]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/irqs_at_max_priority[0][53]} ]] + + + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe62] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62] +connect_debug_port u_ila_0/probe62 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HADDR[0]} {wallypipelinedsoc/core/ebu.ebu/HADDR[1]} {wallypipelinedsoc/core/ebu.ebu/HADDR[2]} {wallypipelinedsoc/core/ebu.ebu/HADDR[3]} {wallypipelinedsoc/core/ebu.ebu/HADDR[4]} {wallypipelinedsoc/core/ebu.ebu/HADDR[5]} {wallypipelinedsoc/core/ebu.ebu/HADDR[6]} {wallypipelinedsoc/core/ebu.ebu/HADDR[7]} {wallypipelinedsoc/core/ebu.ebu/HADDR[8]} {wallypipelinedsoc/core/ebu.ebu/HADDR[9]} {wallypipelinedsoc/core/ebu.ebu/HADDR[10]} {wallypipelinedsoc/core/ebu.ebu/HADDR[11]} {wallypipelinedsoc/core/ebu.ebu/HADDR[12]} {wallypipelinedsoc/core/ebu.ebu/HADDR[13]} {wallypipelinedsoc/core/ebu.ebu/HADDR[14]} {wallypipelinedsoc/core/ebu.ebu/HADDR[15]} {wallypipelinedsoc/core/ebu.ebu/HADDR[16]} {wallypipelinedsoc/core/ebu.ebu/HADDR[17]} {wallypipelinedsoc/core/ebu.ebu/HADDR[18]} {wallypipelinedsoc/core/ebu.ebu/HADDR[19]} {wallypipelinedsoc/core/ebu.ebu/HADDR[20]} {wallypipelinedsoc/core/ebu.ebu/HADDR[21]} {wallypipelinedsoc/core/ebu.ebu/HADDR[22]} {wallypipelinedsoc/core/ebu.ebu/HADDR[23]} {wallypipelinedsoc/core/ebu.ebu/HADDR[24]} {wallypipelinedsoc/core/ebu.ebu/HADDR[25]} {wallypipelinedsoc/core/ebu.ebu/HADDR[26]} {wallypipelinedsoc/core/ebu.ebu/HADDR[27]} {wallypipelinedsoc/core/ebu.ebu/HADDR[28]} {wallypipelinedsoc/core/ebu.ebu/HADDR[29]} {wallypipelinedsoc/core/ebu.ebu/HADDR[30]} {wallypipelinedsoc/core/ebu.ebu/HADDR[31]}]] + + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe63] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63] +connect_debug_port u_ila_0/probe63 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HREADY}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe64] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64] +connect_debug_port u_ila_0/probe64 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HRESP}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe65] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65] +connect_debug_port u_ila_0/probe65 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HWRITE}]] + +create_debug_port u_ila_0 probe +set_property port_width 3 [get_debug_ports u_ila_0/probe66] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66] +connect_debug_port u_ila_0/probe66 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HSIZE[0]} {wallypipelinedsoc/core/ebu.ebu/HSIZE[1]} {wallypipelinedsoc/core/ebu.ebu/HSIZE[2]}]] + +create_debug_port u_ila_0 probe +set_property port_width 3 [get_debug_ports u_ila_0/probe67] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67] +connect_debug_port u_ila_0/probe67 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HBURST[0]} {wallypipelinedsoc/core/ebu.ebu/HBURST[1]} {wallypipelinedsoc/core/ebu.ebu/HBURST[2]}]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe68] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe68] +connect_debug_port u_ila_0/probe68 [get_nets [list {wallypipelinedsoc/core/ebu.ebu/HPROT[0]} {wallypipelinedsoc/core/ebu.ebu/HPROT[1]} {wallypipelinedsoc/core/ebu.ebu/HPROT[2]} {wallypipelinedsoc/core/ebu.ebu/HPROT[3]}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe69] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69] +connect_debug_port u_ila_0/probe69 [get_nets [list {wallypipelinedsoc/core/priv.priv/InterruptM}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe70] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70] +connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsoc/core/lsu/ITLBMissF]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe71] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe71] +connect_debug_port u_ila_0/probe71 [get_nets [list wallypipelinedsoc/core/lsu/DTLBMissM]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe72] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe72] +connect_debug_port u_ila_0/probe72 [get_nets [list wallypipelinedsoc/core/lsu/ITLBWriteF]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe73] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe73] +connect_debug_port u_ila_0/probe73 [get_nets [list wallypipelinedsoc/core/lsu/DTLBWriteM]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe74] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe74] +connect_debug_port u_ila_0/probe74 [get_nets [list {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[0]} {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[1]} {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[2]} {wallypipelinedsoc/core/lsu/hptw.hptw/WalkerState[3]}]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe75] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe75] +connect_debug_port u_ila_0/probe75 [get_nets [list {wallypipelinedsoc/core/SrcAM[0]} {wallypipelinedsoc/core/SrcAM[1]} {wallypipelinedsoc/core/SrcAM[2]} {wallypipelinedsoc/core/SrcAM[3]} {wallypipelinedsoc/core/SrcAM[4]} {wallypipelinedsoc/core/SrcAM[5]} {wallypipelinedsoc/core/SrcAM[6]} {wallypipelinedsoc/core/SrcAM[7]} {wallypipelinedsoc/core/SrcAM[8]} {wallypipelinedsoc/core/SrcAM[9]} {wallypipelinedsoc/core/SrcAM[10]} {wallypipelinedsoc/core/SrcAM[11]} {wallypipelinedsoc/core/SrcAM[12]} {wallypipelinedsoc/core/SrcAM[13]} {wallypipelinedsoc/core/SrcAM[14]} {wallypipelinedsoc/core/SrcAM[15]} {wallypipelinedsoc/core/SrcAM[16]} {wallypipelinedsoc/core/SrcAM[17]} {wallypipelinedsoc/core/SrcAM[18]} {wallypipelinedsoc/core/SrcAM[19]} {wallypipelinedsoc/core/SrcAM[20]} {wallypipelinedsoc/core/SrcAM[21]} {wallypipelinedsoc/core/SrcAM[22]} {wallypipelinedsoc/core/SrcAM[23]} {wallypipelinedsoc/core/SrcAM[24]} {wallypipelinedsoc/core/SrcAM[25]} {wallypipelinedsoc/core/SrcAM[26]} {wallypipelinedsoc/core/SrcAM[27]} {wallypipelinedsoc/core/SrcAM[28]} {wallypipelinedsoc/core/SrcAM[29]} {wallypipelinedsoc/core/SrcAM[30]} {wallypipelinedsoc/core/SrcAM[31]} {wallypipelinedsoc/core/SrcAM[32]} {wallypipelinedsoc/core/SrcAM[33]} {wallypipelinedsoc/core/SrcAM[34]} {wallypipelinedsoc/core/SrcAM[35]} {wallypipelinedsoc/core/SrcAM[36]} {wallypipelinedsoc/core/SrcAM[37]} {wallypipelinedsoc/core/SrcAM[38]} {wallypipelinedsoc/core/SrcAM[39]} {wallypipelinedsoc/core/SrcAM[40]} {wallypipelinedsoc/core/SrcAM[41]} {wallypipelinedsoc/core/SrcAM[42]} {wallypipelinedsoc/core/SrcAM[43]} {wallypipelinedsoc/core/SrcAM[44]} {wallypipelinedsoc/core/SrcAM[45]} {wallypipelinedsoc/core/SrcAM[46]} {wallypipelinedsoc/core/SrcAM[47]} {wallypipelinedsoc/core/SrcAM[48]} {wallypipelinedsoc/core/SrcAM[49]} {wallypipelinedsoc/core/SrcAM[50]} {wallypipelinedsoc/core/SrcAM[51]} {wallypipelinedsoc/core/SrcAM[52]} {wallypipelinedsoc/core/SrcAM[53]} {wallypipelinedsoc/core/SrcAM[54]} {wallypipelinedsoc/core/SrcAM[55]} {wallypipelinedsoc/core/SrcAM[56]} {wallypipelinedsoc/core/SrcAM[57]} {wallypipelinedsoc/core/SrcAM[58]} {wallypipelinedsoc/core/SrcAM[59]} {wallypipelinedsoc/core/SrcAM[60]} {wallypipelinedsoc/core/SrcAM[61]} {wallypipelinedsoc/core/SrcAM[62]} {wallypipelinedsoc/core/SrcAM[63]}]] + + +create_debug_port u_ila_0 probe +set_property port_width 56 [get_debug_ports u_ila_0/probe76] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe76] +connect_debug_port u_ila_0/probe76 [get_nets [list {wallypipelinedsoc/core/ifu/PCPF[0]} {wallypipelinedsoc/core/ifu/PCPF[1]} {wallypipelinedsoc/core/ifu/PCPF[2]} {wallypipelinedsoc/core/ifu/PCPF[3]} {wallypipelinedsoc/core/ifu/PCPF[4]} {wallypipelinedsoc/core/ifu/PCPF[5]} {wallypipelinedsoc/core/ifu/PCPF[6]} {wallypipelinedsoc/core/ifu/PCPF[7]} {wallypipelinedsoc/core/ifu/PCPF[8]} {wallypipelinedsoc/core/ifu/PCPF[9]} {wallypipelinedsoc/core/ifu/PCPF[10]} {wallypipelinedsoc/core/ifu/PCPF[11]} {wallypipelinedsoc/core/ifu/PCPF[12]} {wallypipelinedsoc/core/ifu/PCPF[13]} {wallypipelinedsoc/core/ifu/PCPF[14]} {wallypipelinedsoc/core/ifu/PCPF[15]} {wallypipelinedsoc/core/ifu/PCPF[16]} {wallypipelinedsoc/core/ifu/PCPF[17]} {wallypipelinedsoc/core/ifu/PCPF[18]} {wallypipelinedsoc/core/ifu/PCPF[19]} {wallypipelinedsoc/core/ifu/PCPF[20]} {wallypipelinedsoc/core/ifu/PCPF[21]} {wallypipelinedsoc/core/ifu/PCPF[22]} {wallypipelinedsoc/core/ifu/PCPF[23]} {wallypipelinedsoc/core/ifu/PCPF[24]} {wallypipelinedsoc/core/ifu/PCPF[25]} {wallypipelinedsoc/core/ifu/PCPF[26]} {wallypipelinedsoc/core/ifu/PCPF[27]} {wallypipelinedsoc/core/ifu/PCPF[28]} {wallypipelinedsoc/core/ifu/PCPF[29]} {wallypipelinedsoc/core/ifu/PCPF[30]} {wallypipelinedsoc/core/ifu/PCPF[31]} {wallypipelinedsoc/core/ifu/PCPF[32]} {wallypipelinedsoc/core/ifu/PCPF[33]} {wallypipelinedsoc/core/ifu/PCPF[34]} {wallypipelinedsoc/core/ifu/PCPF[35]} {wallypipelinedsoc/core/ifu/PCPF[36]} {wallypipelinedsoc/core/ifu/PCPF[37]} {wallypipelinedsoc/core/ifu/PCPF[38]} {wallypipelinedsoc/core/ifu/PCPF[39]} {wallypipelinedsoc/core/ifu/PCPF[40]} {wallypipelinedsoc/core/ifu/PCPF[41]} {wallypipelinedsoc/core/ifu/PCPF[42]} {wallypipelinedsoc/core/ifu/PCPF[43]} {wallypipelinedsoc/core/ifu/PCPF[44]} {wallypipelinedsoc/core/ifu/PCPF[45]} {wallypipelinedsoc/core/ifu/PCPF[46]} {wallypipelinedsoc/core/ifu/PCPF[47]} {wallypipelinedsoc/core/ifu/PCPF[48]} {wallypipelinedsoc/core/ifu/PCPF[49]} {wallypipelinedsoc/core/ifu/PCPF[50]} {wallypipelinedsoc/core/ifu/PCPF[51]} {wallypipelinedsoc/core/ifu/PCPF[52]} {wallypipelinedsoc/core/ifu/PCPF[53]} {wallypipelinedsoc/core/ifu/PCPF[54]} {wallypipelinedsoc/core/ifu/PCPF[55]} ]] + + + +create_debug_port u_ila_0 probe +set_property port_width 3 [get_debug_ports u_ila_0/probe77] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe77] +connect_debug_port u_ila_0/probe77 [get_nets [list {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsoc/core/ifu/bus.icache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe78] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe78] +connect_debug_port u_ila_0/probe78 [get_nets [list wallypipelinedsoc/core/ifu/Spill.spill/CurrState[0] ]] + + +create_debug_port u_ila_0 probe +set_property port_width 3 [get_debug_ports u_ila_0/probe79] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe79] +connect_debug_port u_ila_0/probe79 [get_nets [list {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[0]} {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[1]} {wallypipelinedsoc/core/lsu/bus.dcache.ahbcacheinterface/AHBBuscachefsm/CurrState[2]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 7 [get_debug_ports u_ila_0/probe80] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe80] +connect_debug_port u_ila_0/probe80 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[1][1]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[1][2]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[1][3]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[1][4]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[1][5]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[1][6]} {wallypipelinedsoc/uncoregen.uncore/plic.plic/threshMask[1][7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe81] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe81] +connect_debug_port u_ila_0/probe81 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe82] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe82] +connect_debug_port u_ila_0/probe82 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe83] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe83] +connect_debug_port u_ila_0/probe83 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe84] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe84] +connect_debug_port u_ila_0/probe84 [get_nets [list wallypipelinedsoc/core/ieu/dp/RegWriteW]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe85] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe85] +connect_debug_port u_ila_0/probe85 [get_nets [list {wallypipelinedsoc/core/priv.priv/CSRWriteM} ]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe86] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe86] +connect_debug_port u_ila_0/probe86 [get_nets [list {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[0]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[1]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[2]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[3]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[4]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[5]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[6]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[7]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[8]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[9]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[10]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[11]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[12]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[13]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[14]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[15]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[16]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[17]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[18]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[19]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[20]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[21]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[22]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[23]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[24]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[25]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[26]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[27]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[28]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[29]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[30]} {wallypipelinedsoc/core/ifu/PostSpillInstrRawF[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe87] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe87] +connect_debug_port u_ila_0/probe87 [get_nets [list {wallypipelinedsoc/core/ifu/PCNextF[0]} {wallypipelinedsoc/core/ifu/PCNextF[1]} {wallypipelinedsoc/core/ifu/PCNextF[2]} {wallypipelinedsoc/core/ifu/PCNextF[3]} {wallypipelinedsoc/core/ifu/PCNextF[4]} {wallypipelinedsoc/core/ifu/PCNextF[5]} {wallypipelinedsoc/core/ifu/PCNextF[6]} {wallypipelinedsoc/core/ifu/PCNextF[7]} {wallypipelinedsoc/core/ifu/PCNextF[8]} {wallypipelinedsoc/core/ifu/PCNextF[9]} {wallypipelinedsoc/core/ifu/PCNextF[10]} {wallypipelinedsoc/core/ifu/PCNextF[11]} {wallypipelinedsoc/core/ifu/PCNextF[12]} {wallypipelinedsoc/core/ifu/PCNextF[13]} {wallypipelinedsoc/core/ifu/PCNextF[14]} {wallypipelinedsoc/core/ifu/PCNextF[15]} {wallypipelinedsoc/core/ifu/PCNextF[16]} {wallypipelinedsoc/core/ifu/PCNextF[17]} {wallypipelinedsoc/core/ifu/PCNextF[18]} {wallypipelinedsoc/core/ifu/PCNextF[19]} {wallypipelinedsoc/core/ifu/PCNextF[20]} {wallypipelinedsoc/core/ifu/PCNextF[21]} {wallypipelinedsoc/core/ifu/PCNextF[22]} {wallypipelinedsoc/core/ifu/PCNextF[23]} {wallypipelinedsoc/core/ifu/PCNextF[24]} {wallypipelinedsoc/core/ifu/PCNextF[25]} {wallypipelinedsoc/core/ifu/PCNextF[26]} {wallypipelinedsoc/core/ifu/PCNextF[27]} {wallypipelinedsoc/core/ifu/PCNextF[28]} {wallypipelinedsoc/core/ifu/PCNextF[29]} {wallypipelinedsoc/core/ifu/PCNextF[30]} {wallypipelinedsoc/core/ifu/PCNextF[31]} {wallypipelinedsoc/core/ifu/PCNextF[32]} {wallypipelinedsoc/core/ifu/PCNextF[33]} {wallypipelinedsoc/core/ifu/PCNextF[34]} {wallypipelinedsoc/core/ifu/PCNextF[35]} {wallypipelinedsoc/core/ifu/PCNextF[36]} {wallypipelinedsoc/core/ifu/PCNextF[37]} {wallypipelinedsoc/core/ifu/PCNextF[38]} {wallypipelinedsoc/core/ifu/PCNextF[39]} {wallypipelinedsoc/core/ifu/PCNextF[40]} {wallypipelinedsoc/core/ifu/PCNextF[41]} {wallypipelinedsoc/core/ifu/PCNextF[42]} {wallypipelinedsoc/core/ifu/PCNextF[43]} {wallypipelinedsoc/core/ifu/PCNextF[44]} {wallypipelinedsoc/core/ifu/PCNextF[45]} {wallypipelinedsoc/core/ifu/PCNextF[46]} {wallypipelinedsoc/core/ifu/PCNextF[47]} {wallypipelinedsoc/core/ifu/PCNextF[48]} {wallypipelinedsoc/core/ifu/PCNextF[49]} {wallypipelinedsoc/core/ifu/PCNextF[50]} {wallypipelinedsoc/core/ifu/PCNextF[51]} {wallypipelinedsoc/core/ifu/PCNextF[52]} {wallypipelinedsoc/core/ifu/PCNextF[53]} {wallypipelinedsoc/core/ifu/PCNextF[54]} {wallypipelinedsoc/core/ifu/PCNextF[55]} {wallypipelinedsoc/core/ifu/PCNextF[56]} {wallypipelinedsoc/core/ifu/PCNextF[57]} {wallypipelinedsoc/core/ifu/PCNextF[58]} {wallypipelinedsoc/core/ifu/PCNextF[59]} {wallypipelinedsoc/core/ifu/PCNextF[60]} {wallypipelinedsoc/core/ifu/PCNextF[61]} {wallypipelinedsoc/core/ifu/PCNextF[62]} {wallypipelinedsoc/core/ifu/PCNextF[63]}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe88] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe88] +connect_debug_port u_ila_0/probe88 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MExtInt}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe89] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe89] +connect_debug_port u_ila_0/probe89 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SExtInt} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe90] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe90] +connect_debug_port u_ila_0/probe90 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MTimerInt} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe91] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe91] +connect_debug_port u_ila_0/probe91 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MSwInt} ]] + +create_debug_port u_ila_0 probe +set_property port_width 12 [get_debug_ports u_ila_0/probe92] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe92] +connect_debug_port u_ila_0/probe92 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 12 [get_debug_ports u_ila_0/probe93] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe93] +connect_debug_port u_ila_0/probe93 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[11]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe94] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe94] +connect_debug_port u_ila_0/probe94 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSTATUS_REGW[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe95] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe95] +connect_debug_port u_ila_0/probe95 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/SSTATUS_REGW[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe96] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe96] +connect_debug_port u_ila_0/probe96 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[32]} 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{wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[2]__0[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe97] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe97] +connect_debug_port u_ila_0/probe97 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[23]} 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{wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe98] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe98] +connect_debug_port u_ila_0/probe98 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs.csrs/SSCRATCH_REGW[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe99] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe99] +connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 49 [get_debug_ports u_ila_0/probe100] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe100] +connect_debug_port u_ila_0/probe100 [get_nets [list {wallypipelinedsoc/core/lsu/PTE[0]} {wallypipelinedsoc/core/lsu/PTE[3]} {wallypipelinedsoc/core/lsu/PTE[4]} {wallypipelinedsoc/core/lsu/PTE[5]} {wallypipelinedsoc/core/lsu/PTE[6]} {wallypipelinedsoc/core/lsu/PTE[10]} {wallypipelinedsoc/core/lsu/PTE[11]} {wallypipelinedsoc/core/lsu/PTE[12]} {wallypipelinedsoc/core/lsu/PTE[13]} {wallypipelinedsoc/core/lsu/PTE[14]} {wallypipelinedsoc/core/lsu/PTE[15]} {wallypipelinedsoc/core/lsu/PTE[16]} {wallypipelinedsoc/core/lsu/PTE[17]} {wallypipelinedsoc/core/lsu/PTE[18]} {wallypipelinedsoc/core/lsu/PTE[19]} {wallypipelinedsoc/core/lsu/PTE[20]} {wallypipelinedsoc/core/lsu/PTE[21]} {wallypipelinedsoc/core/lsu/PTE[22]} {wallypipelinedsoc/core/lsu/PTE[23]} {wallypipelinedsoc/core/lsu/PTE[24]} {wallypipelinedsoc/core/lsu/PTE[25]} {wallypipelinedsoc/core/lsu/PTE[26]} {wallypipelinedsoc/core/lsu/PTE[27]} {wallypipelinedsoc/core/lsu/PTE[28]} {wallypipelinedsoc/core/lsu/PTE[29]} {wallypipelinedsoc/core/lsu/PTE[30]} {wallypipelinedsoc/core/lsu/PTE[31]} {wallypipelinedsoc/core/lsu/PTE[32]} {wallypipelinedsoc/core/lsu/PTE[33]} {wallypipelinedsoc/core/lsu/PTE[34]} {wallypipelinedsoc/core/lsu/PTE[35]} {wallypipelinedsoc/core/lsu/PTE[36]} {wallypipelinedsoc/core/lsu/PTE[37]} {wallypipelinedsoc/core/lsu/PTE[38]} {wallypipelinedsoc/core/lsu/PTE[39]} {wallypipelinedsoc/core/lsu/PTE[40]} {wallypipelinedsoc/core/lsu/PTE[41]} {wallypipelinedsoc/core/lsu/PTE[42]} {wallypipelinedsoc/core/lsu/PTE[43]} {wallypipelinedsoc/core/lsu/PTE[44]} {wallypipelinedsoc/core/lsu/PTE[45]} {wallypipelinedsoc/core/lsu/PTE[46]} {wallypipelinedsoc/core/lsu/PTE[47]} {wallypipelinedsoc/core/lsu/PTE[48]} {wallypipelinedsoc/core/lsu/PTE[49]} {wallypipelinedsoc/core/lsu/PTE[50]} {wallypipelinedsoc/core/lsu/PTE[51]} {wallypipelinedsoc/core/lsu/PTE[52]} {wallypipelinedsoc/core/lsu/PTE[53]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe101] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe101] +connect_debug_port u_ila_0/probe101 [get_nets [list {wallypipelinedsoc/core/lsu/hptw.hptw/ValidNonLeafPTE}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe102] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe102] +connect_debug_port u_ila_0/probe102 [get_nets [list {wallypipelinedsoc/core/lsu/hptw.hptw/ValidLeafPTE}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe103] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe103] +connect_debug_port u_ila_0/probe103 [get_nets [list {wallypipelinedsoc/core/lsu/hptw.hptw/ValidPTE}]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe104] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe104] +connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsoc/core/lsu/hptw.hptw/LeafPTE}]] + + +create_debug_port u_ila_0 probe +set_property port_width 48 [get_debug_ports u_ila_0/probe105] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe105] +connect_debug_port u_ila_0/probe105 [get_nets [list {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[0]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[1]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[2]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[3]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[4]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[5]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[6]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[7]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[8]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[9]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[10]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[11]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[12]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[13]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[14]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[15]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[16]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[17]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[18]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[19]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[20]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[21]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[22]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[23]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[24]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[25]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[26]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[27]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[28]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[29]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[30]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[31]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[32]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[33]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[34]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[35]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[36]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[37]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[38]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[39]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[40]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[41]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[42]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[43]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[60]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[61]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[62]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[63]}]] diff --git a/fpga/constraints/marked_debug_all.txt b/fpga/constraints/marked_debug_all.txt index 3973fc451..1ddec51c9 100644 --- a/fpga/constraints/marked_debug_all.txt +++ b/fpga/constraints/marked_debug_all.txt @@ -45,6 +45,7 @@ ifu/ifu.sv: logic PCPF ifu/ifu.sv: logic PostSpillInstrRawF mmu/hptw.sv: logic ITLBWriteF mmu/hptw.sv: statetype WalkerState +mmu/hptw.sv: logic ValidPTE privileged/csrs.sv: logic CSRSReadValM privileged/csrs.sv: logic SEPC_REGW privileged/csrs.sv: logic MIP_REGW diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 4939881a9..eff0a6cb9 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -19,7 +19,7 @@ read_verilog -sv ../src/CopiedFiles_do_not_add_to_repo/cvw.sv if {$board=="ArtyA7"} { read_verilog {../src/fpgaTopArtyA7.sv} } else { - read_verilog {../src/fpgaTop.v} + read_verilog {../src/fpgaTop.sv} } # read in ip @@ -93,7 +93,7 @@ if {$board=="ArtyA7"} { } else { # source ../constraints/vcu-small-debug.xdc - source ../constraints/debug4.xdc + source ../constraints/debug6.xdc } diff --git a/fpga/renumber.py b/fpga/renumber.py new file mode 100755 index 000000000..adf625920 --- /dev/null +++ b/fpga/renumber.py @@ -0,0 +1,33 @@ +#!/usr/bin/python3 +import sys +import re + +def usage(): + print("Usage: ./renumber.py ") + +def main(args): + if (len(args) != 2): + usage() + exit() + + probenum = 0 + countLines = 1 + + with open(args[0],'r') as xdcfile, open(args[1], 'w') as outfile: + Lines = xdcfile.readlines() + for line in Lines: + t = re.sub("probe[0-9]+", f"probe{probenum}",line) + + if line.find("probe") >= 0: + countLines = countLines + 1 + + if countLines == 4: + countLines = 0 + probenum = probenum + 1 + + outfile.write(t) + + + +if __name__ == '__main__': + main(sys.argv[1:]) diff --git a/fpga/src/fpgaTop.sv b/fpga/src/fpgaTop.sv new file mode 100644 index 000000000..f07bd5240 --- /dev/null +++ b/fpga/src/fpgaTop.sv @@ -0,0 +1,1130 @@ +/////////////////////////////////////////// +// fpgaTop.sv +// +// Written: ross1728@gmail.com November 17, 2021 +// Modified: +// +// Purpose: This is a top level for the fpga's implementation of wally. +// Instantiates wallysoc, ddr4, abh lite to axi converters, pll, etc +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "config.vh" + +import cvw::*; + +module fpgaTop + (input default_250mhz_clk1_0_n, + input default_250mhz_clk1_0_p, + input reset, + input south_rst, + + input [3:0] GPI, + output [4:0] GPO, + + input UARTSin, + output UARTSout, + + inout [3:0] SDCDat, + output SDCCLK, + inout SDCCmd, + input SDCCD, + + output calib, + output cpu_reset, + output ahblite_resetn, + + output [16 : 0] c0_ddr4_adr, + output [1 : 0] c0_ddr4_ba, + output [0 : 0] c0_ddr4_cke, + output [0 : 0] c0_ddr4_cs_n, + inout [7 : 0] c0_ddr4_dm_dbi_n, + inout [63 : 0] c0_ddr4_dq, + inout [7 : 0] c0_ddr4_dqs_c, + inout [7 : 0] c0_ddr4_dqs_t, + output [0 : 0] c0_ddr4_odt, + output [0 : 0] c0_ddr4_bg, + output c0_ddr4_reset_n, + output c0_ddr4_act_n, + output [0 : 0] c0_ddr4_ck_c, + output [0 : 0] c0_ddr4_ck_t + ); + + wire CPUCLK; + wire c0_ddr4_ui_clk_sync_rst; + wire bus_struct_reset; + wire peripheral_reset; + wire interconnect_aresetn; + wire peripheral_aresetn; + wire mb_reset; + + wire HCLKOpen; + wire HRESETnOpen; + wire [64-1:0] HRDATAEXT; + wire HREADYEXT; + wire HRESPEXT; + (* mark_debug = "true" *) wire HSELEXT; + (* mark_debug = "true" *) wire HSELEXTSDC; // TEMP BOOT SIGNAL - JACOB + wire [55:0] HADDR; + wire [64-1:0] HWDATA; + wire [64/8-1:0] HWSTRB; + wire HWRITE; + wire [2:0] HSIZE; + wire [2:0] HBURST; + wire [1:0] HTRANS; + wire HREADY; + wire [3:0] HPROT; + wire HMASTLOCK; + + + + wire [31:0] GPIOIN, GPIOOUT, GPIOEN; + + // Old SDC connections + // wire SDCCmdIn; + // wire SDCCmdOE; + // wire SDCCmdOut; + + (* mark_debug = "true" *)wire [3:0] m_axi_awid; + (* mark_debug = "true" *)wire [7:0] m_axi_awlen; + (* mark_debug = "true" *)wire [2:0] m_axi_awsize; + (* mark_debug = "true" *)wire [1:0] m_axi_awburst; + (* mark_debug = "true" *)wire [3:0] m_axi_awcache; + (* mark_debug = "true" *)wire [31:0] m_axi_awaddr; + (* mark_debug = "true" *)wire [2:0] m_axi_awprot; + (* mark_debug = "true" *)wire m_axi_awvalid; + (* mark_debug = "true" *)wire m_axi_awready; + (* mark_debug = "true" *)wire m_axi_awlock; + (* mark_debug = "true" *)wire [63:0] m_axi_wdata; + (* mark_debug = "true" *)wire [7:0] m_axi_wstrb; + (* mark_debug = "true" *)wire m_axi_wlast; + (* mark_debug = "true" *)wire m_axi_wvalid; + (* mark_debug = "true" *)wire m_axi_wready; + (* mark_debug = "true" *)wire [3:0] m_axi_bid; + (* mark_debug = "true" *)wire [1:0] m_axi_bresp; + (* mark_debug = "true" *)wire m_axi_bvalid; + (* mark_debug = "true" *)wire m_axi_bready; + (* mark_debug = "true" *)wire [3:0] m_axi_arid; + (* mark_debug = "true" *)wire [7:0] m_axi_arlen; + (* mark_debug = "true" *)wire [2:0] m_axi_arsize; + (* mark_debug = "true" *)wire [1:0] m_axi_arburst; + (* mark_debug = "true" *)wire [2:0] m_axi_arprot; + (* mark_debug = "true" *)wire [3:0] m_axi_arcache; + (* mark_debug = "true" *)wire m_axi_arvalid; + (* mark_debug = "true" *)wire [31:0] m_axi_araddr; + (* mark_debug = "true" *)wire m_axi_arlock; + (* mark_debug = "true" *)wire m_axi_arready; + (* mark_debug = "true" *)wire [3:0] m_axi_rid; + (* mark_debug = "true" *)wire [63:0] m_axi_rdata; + (* mark_debug = "true" *)wire [1:0] m_axi_rresp; + (* mark_debug = "true" *)wire m_axi_rvalid; + (* mark_debug = "true" *)wire m_axi_rlast; + (* mark_debug = "true" *)wire m_axi_rready; + + // Extra Bus signals + wire [3:0] BUS_axi_arregion; + wire [3:0] BUS_axi_arqos; + wire [3:0] BUS_axi_awregion; + wire [3:0] BUS_axi_awqos; + + // Bus signals + wire [3:0] BUS_axi_awid; + wire [7:0] BUS_axi_awlen; + wire [2:0] BUS_axi_awsize; + wire [1:0] BUS_axi_awburst; + wire [3:0] BUS_axi_awcache; + wire [30:0] BUS_axi_awaddr; + wire [2:0] BUS_axi_awprot; + wire BUS_axi_awvalid; + wire BUS_axi_awready; + wire BUS_axi_awlock; + wire [63:0] BUS_axi_wdata; + wire [7:0] BUS_axi_wstrb; + wire BUS_axi_wlast; + wire BUS_axi_wvalid; + wire BUS_axi_wready; + wire [3:0] BUS_axi_bid; + wire [1:0] BUS_axi_bresp; + wire BUS_axi_bvalid; + wire BUS_axi_bready; + wire [3:0] BUS_axi_arid; + wire [7:0] BUS_axi_arlen; + wire [2:0] BUS_axi_arsize; + wire [1:0] BUS_axi_arburst; + wire [2:0] BUS_axi_arprot; + wire [3:0] BUS_axi_arcache; + wire BUS_axi_arvalid; + wire [30:0] BUS_axi_araddr; + wire BUS_axi_arlock; + wire BUS_axi_arready; + wire [3:0] BUS_axi_rid; + wire [63:0] BUS_axi_rdata; + wire [1:0] BUS_axi_rresp; + wire BUS_axi_rvalid; + wire BUS_axi_rlast; + wire BUS_axi_rready; + + wire BUSCLK; + + + wire c0_init_calib_complete; + wire dbg_clk; + wire [511 : 0] dbg_bus; + + wire CLK208; + + + // Crossbar to Bus ------------------------------------------------ + + (* mark_debug = "true" *)wire s00_axi_aclk; + (* mark_debug = "true" *)wire s00_axi_aresetn; + (* mark_debug = "true" *)wire [3:0] s00_axi_awid; + (* mark_debug = "true" *)wire [31:0]s00_axi_awaddr; + (* mark_debug = "true" *)wire [7:0]s00_axi_awlen; + (* mark_debug = "true" *)wire [2:0]s00_axi_awsize; + (* mark_debug = "true" *)wire [1:0]s00_axi_awburst; + (* mark_debug = "true" *)wire [0:0]s00_axi_awlock; + (* mark_debug = "true" *)wire [3:0]s00_axi_awcache; + (* mark_debug = "true" *)wire [2:0]s00_axi_awprot; + (* mark_debug = "true" *)wire [3:0]s00_axi_awregion; + (* mark_debug = "true" *)wire [3:0]s00_axi_awqos; + (* mark_debug = "true" *) wire s00_axi_awvalid; + (* mark_debug = "true" *) wire s00_axi_awready; + (* mark_debug = "true" *)wire [63:0]s00_axi_wdata; + (* mark_debug = "true" *)wire [7:0]s00_axi_wstrb; + (* mark_debug = "true" *)wire s00_axi_wlast; + (* mark_debug = "true" *)wire s00_axi_wvalid; + (* mark_debug = "true" *)wire s00_axi_wready; + (* mark_debug = "true" *)wire [1:0]s00_axi_bresp; + (* mark_debug = "true" *)wire s00_axi_bvalid; + (* mark_debug = "true" *)wire s00_axi_bready; + (* mark_debug = "true" *)wire [31:0]s00_axi_araddr; + (* mark_debug = "true" *)wire [7:0]s00_axi_arlen; + (* mark_debug = "true" *)wire [2:0]s00_axi_arsize; + (* mark_debug = "true" *)wire [1:0]s00_axi_arburst; + (* mark_debug = "true" *)wire [0:0]s00_axi_arlock; + (* mark_debug = "true" *)wire [3:0]s00_axi_arcache; + (* mark_debug = "true" *)wire [2:0]s00_axi_arprot; + (* mark_debug = "true" *)wire [3:0]s00_axi_arregion; + (* mark_debug = "true" *)wire [3:0]s00_axi_arqos; + (* mark_debug = "true" *)wire s00_axi_arvalid; + (* mark_debug = "true" *)wire s00_axi_arready; + (* mark_debug = "true" *)wire [63:0]s00_axi_rdata; + (* mark_debug = "true" *)wire [1:0]s00_axi_rresp; + (* mark_debug = "true" *)wire s00_axi_rlast; + (* mark_debug = "true" *)wire s00_axi_rvalid; + (* mark_debug = "true" *)wire s00_axi_rready; + + (* mark_debug = "true" *)wire [3:0] s00_axi_bid; + (* mark_debug = "true" *)wire [3:0] s00_axi_rid; + + // 64to32 dwidth converter input interface------------------------- + wire s01_axi_aclk; + wire s01_axi_aresetn; + wire [3:0]s01_axi_awid; + wire [31:0]s01_axi_awaddr; + wire [7:0]s01_axi_awlen; + wire [2:0]s01_axi_awsize; + wire [1:0]s01_axi_awburst; + wire [0:0]s01_axi_awlock; + wire [3:0]s01_axi_awcache; + wire [2:0]s01_axi_awprot; + wire [3:0]s01_axi_awregion; + wire [3:0]s01_axi_awqos; // qos signals need to be 0 for SDC + (* mark_debug = "true" *) wire s01_axi_awvalid; + (* mark_debug = "true" *) wire s01_axi_awready; + wire [63:0]s01_axi_wdata; + wire [7:0]s01_axi_wstrb; + wire s01_axi_wlast; + wire s01_axi_wvalid; + wire s01_axi_wready; + wire [1:0]s01_axi_bresp; + wire s01_axi_bvalid; + wire s01_axi_bready; + wire [31:0]s01_axi_araddr; + wire [7:0]s01_axi_arlen; + wire [2:0]s01_axi_arsize; + wire [1:0]s01_axi_arburst; + wire [0:0]s01_axi_arlock; + wire [3:0]s01_axi_arcache; + wire [2:0]s01_axi_arprot; + wire [3:0]s01_axi_arregion; + wire [3:0]s01_axi_arqos; // + wire s01_axi_arvalid; + wire s01_axi_arready; + wire [63:0]s01_axi_rdata; + wire [1:0]s01_axi_rresp; + wire s01_axi_rlast; + wire s01_axi_rvalid; + wire s01_axi_rready; + + // Output Interface + wire [31:0]axi4in_axi_awaddr; + wire [7:0]axi4in_axi_awlen; + wire [2:0]axi4in_axi_awsize; + wire [1:0]axi4in_axi_awburst; + wire [0:0]axi4in_axi_awlock; + wire [3:0]axi4in_axi_awcache; + wire [2:0]axi4in_axi_awprot; + wire [3:0]axi4in_axi_awregion; + wire [3:0]axi4in_axi_awqos; + (* mark_debug = "true" *) wire axi4in_axi_awvalid; + (* mark_debug = "true" *) wire axi4in_axi_awready; + wire [31:0]axi4in_axi_wdata; + wire [3:0]axi4in_axi_wstrb; + wire axi4in_axi_wlast; + wire axi4in_axi_wvalid; + wire axi4in_axi_wready; + wire [1:0]axi4in_axi_bresp; + wire axi4in_axi_bvalid; + wire axi4in_axi_bready; + wire [31:0]axi4in_axi_araddr; + wire [7:0]axi4in_axi_arlen; + wire [2:0]axi4in_axi_arsize; + wire [1:0]axi4in_axi_arburst; + wire [0:0]axi4in_axi_arlock; + wire [3:0]axi4in_axi_arcache; + wire [2:0]axi4in_axi_arprot; + wire [3:0]axi4in_axi_arregion; + wire [3:0]axi4in_axi_arqos; + wire axi4in_axi_arvalid; + wire axi4in_axi_arready; + wire [31:0]axi4in_axi_rdata; + wire [1:0]axi4in_axi_rresp; + wire axi4in_axi_rlast; + wire axi4in_axi_rvalid; + wire axi4in_axi_rready; + + // AXI4 to AXI4-Lite Protocol converter output + (* mark_debug = "true" *) wire [31:0]SDCin_axi_awaddr; + (* mark_debug = "true" *) wire [2:0]SDCin_axi_awprot; + (* mark_debug = "true" *) wire SDCin_axi_awvalid; + (* mark_debug = "true" *) wire SDCin_axi_awready; + (* mark_debug = "true" *) wire [31:0]SDCin_axi_wdata; + (* mark_debug = "true" *) wire [3:0]SDCin_axi_wstrb; + (* mark_debug = "true" *) wire SDCin_axi_wvalid; + (* mark_debug = "true" *) wire SDCin_axi_wready; + (* mark_debug = "true" *) wire [1:0]SDCin_axi_bresp; + (* mark_debug = "true" *) wire SDCin_axi_bvalid; + (* mark_debug = "true" *) wire SDCin_axi_bready; + (* mark_debug = "true" *) wire [31:0]SDCin_axi_araddr; + (* mark_debug = "true" *) wire [2:0]SDCin_axi_arprot; + (* mark_debug = "true" *) wire SDCin_axi_arvalid; + (* mark_debug = "true" *) wire SDCin_axi_arready; + (* mark_debug = "true" *) wire [31:0]SDCin_axi_rdata; + (* mark_debug = "true" *) wire [1:0]SDCin_axi_rresp; + (* mark_debug = "true" *) wire SDCin_axi_rvalid; + (* mark_debug = "true" *) wire SDCin_axi_rready; + // ---------------------------------------------------------------- + + // 32to64 dwidth converter input interface ----------------------- + (* mark_debug = "true" *) wire [31:0]SDCout_axi_awaddr; + (* mark_debug = "true" *) wire [7:0]SDCout_axi_awlen; + wire [2:0]SDCout_axi_awsize; + wire [1:0]SDCout_axi_awburst; + wire [0:0]SDCout_axi_awlock; + wire [3:0]SDCout_axi_awcache; + wire [2:0]SDCout_axi_awprot; + wire [3:0]SDCout_axi_awregion; + wire [3:0]SDCout_axi_awqos; + (* mark_debug = "true" *) wire SDCout_axi_awvalid; + (* mark_debug = "true" *) wire SDCout_axi_awready; + (* mark_debug = "true" *) wire [31:0]SDCout_axi_wdata; + wire [3:0]SDCout_axi_wstrb; + (* mark_debug = "true" *) wire SDCout_axi_wlast; + (* mark_debug = "true" *) wire SDCout_axi_wvalid; + (* mark_debug = "true" *)wire SDCout_axi_wready; + (* mark_debug = "true" *) wire [1:0]SDCout_axi_bresp; + (* mark_debug = "true" *) wire SDCout_axi_bvalid; + (* mark_debug = "true" *) wire SDCout_axi_bready; + wire [31:0]SDCout_axi_araddr; + wire [7:0]SDCout_axi_arlen; + wire [2:0]SDCout_axi_arsize; + wire [1:0]SDCout_axi_arburst; + wire [0:0]SDCout_axi_arlock; + wire [3:0]SDCout_axi_arcache; + wire [2:0]SDCout_axi_arprot; + wire [3:0]SDCout_axi_arregion; + wire [3:0]SDCout_axi_arqos; + wire SDCout_axi_arvalid; + wire SDCout_axi_arready; + wire [31:0]SDCout_axi_rdata; + wire [1:0]SDCout_axi_rresp; + wire SDCout_axi_rlast; + wire SDCout_axi_rvalid; + wire SDCout_axi_rready; + + // Output Interface + (* mark_debug = "true" *) wire [3:0]m01_axi_awid; + (* mark_debug = "true" *) wire [31:0]m01_axi_awaddr; + (* mark_debug = "true" *) wire [7:0]m01_axi_awlen; + (* mark_debug = "true" *) wire [2:0]m01_axi_awsize; + (* mark_debug = "true" *) wire [1:0]m01_axi_awburst; + (* mark_debug = "true" *) wire [0:0]m01_axi_awlock; + (* mark_debug = "true" *) wire [3:0]m01_axi_awcache; + (* mark_debug = "true" *) wire [2:0]m01_axi_awprot; + (* mark_debug = "true" *) wire [3:0]m01_axi_awregion; + (* mark_debug = "true" *) wire [3:0]m01_axi_awqos; + (* mark_debug = "true" *) wire m01_axi_awvalid; + (* mark_debug = "true" *) wire m01_axi_awready; + (* mark_debug = "true" *) wire [63:0]m01_axi_wdata; + (* mark_debug = "true" *) wire [7:0]m01_axi_wstrb; + (* mark_debug = "true" *) wire m01_axi_wlast; + (* mark_debug = "true" *) wire m01_axi_wvalid; + (* mark_debug = "true" *) wire m01_axi_wready; + (* mark_debug = "true" *) wire [3:0] m01_axi_bid; + (* mark_debug = "true" *) wire [1:0]m01_axi_bresp; + (* mark_debug = "true" *) wire m01_axi_bvalid; + (* mark_debug = "true" *) wire m01_axi_bready; + (* mark_debug = "true" *) wire [3:0] m01_axi_arid; + (* mark_debug = "true" *) wire [31:0]m01_axi_araddr; + (* mark_debug = "true" *) wire [7:0]m01_axi_arlen; + (* mark_debug = "true" *) wire [2:0]m01_axi_arsize; + (* mark_debug = "true" *) wire [1:0]m01_axi_arburst; + (* mark_debug = "true" *) wire [0:0]m01_axi_arlock; + (* mark_debug = "true" *) wire [3:0]m01_axi_arcache; + (* mark_debug = "true" *) wire [2:0]m01_axi_arprot; + (* mark_debug = "true" *) wire [3:0]m01_axi_arregion; + (* mark_debug = "true" *) wire [3:0]m01_axi_arqos; + (* mark_debug = "true" *) wire m01_axi_arvalid; + (* mark_debug = "true" *) wire m01_axi_arready; + (* mark_debug = "true" *) wire [3:0] m01_axi_rid; + (* mark_debug = "true" *) wire [63:0]m01_axi_rdata; + (* mark_debug = "true" *) wire [1:0]m01_axi_rresp; + (* mark_debug = "true" *) wire m01_axi_rlast; + (* mark_debug = "true" *) wire m01_axi_rvalid; + (* mark_debug = "true" *) wire m01_axi_rready; + + // Old SDC input + // wire [3:0] SDCDatIn; + + // New SDC Command IOBUF connections + wire sd_cmd_i; + wire sd_cmd_reg_o; + wire sd_cmd_reg_t; + + // SD Card Interrupt signal + (* mark_debug = "true" *) wire SDCIntr; + + // New SDC Data IOBUF connections + wire [3:0] sd_dat_i; + wire [3:0] sd_dat_reg_o; + wire sd_dat_reg_t; + + assign GPIOIN = {28'b0, GPI}; + assign GPO = GPIOOUT[4:0]; + assign ahblite_resetn = peripheral_aresetn; + assign cpu_reset = bus_struct_reset; + assign calib = c0_init_calib_complete; + + + + // SD Card Tristate + /* + IOBUF iobufSDCMD(.T(~SDCCmdOE), // iobuf's T is active low + .I(SDCCmdOut), + .O(SDCCmdIn), + .IO(SDCCmd)); + + genvar i; + generate + for (i = 0; i < 4; i = i + 1) begin + IOBUF iobufSDCDat(.T(1'b1), + .I(1'b0), + .O(SDCDatIn[i]), + .IO(SDCDat[i])); + end + endgenerate + */ + + // IOBUFS for new SDC peripheral + IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(SDCCmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t)); + genvar i; + generate + for (i = 0; i < 4; i = i + 1) begin + IOBUF iobufSDCDat(.T(sd_dat_reg_t), + .I(sd_dat_reg_o[i]), + .O(sd_dat_i[i]), + .IO(SDCDat[i]) ); + end + endgenerate + + // IOBUF IOBUF_dat0 (.O(sd_dat_i[0]), .IO(sdio_dat[0]), .I(sd_dat_reg_o[0]), .T(sd_dat_reg_t)); + // IOBUF IOBUF_dat1 (.O(sd_dat_i[1]), .IO(sdio_dat[1]), .I(sd_dat_reg_o[1]), .T(sd_dat_reg_t)); + // IOBUF IOBUF_dat2 (.O(sd_dat_i[2]), .IO(sdio_dat[2]), .I(sd_dat_reg_o[2]), .T(sd_dat_reg_t)); + // IOBUF IOBUF_dat3 (.O(sd_dat_i[3]), .IO(sdio_dat[3]), .I(sd_dat_reg_o[3]), .T(sd_dat_reg_t)); + + + + // reset controller XILINX IP + xlnx_proc_sys_reset xlnx_proc_sys_reset_0 + (.slowest_sync_clk(CPUCLK), + .ext_reset_in(c0_ddr4_ui_clk_sync_rst), + .aux_reset_in(south_rst), + .mb_debug_sys_rst(1'b0), + .dcm_locked(c0_init_calib_complete), + .mb_reset(mb_reset), //open + .bus_struct_reset(bus_struct_reset), + .peripheral_reset(peripheral_reset), //open + .interconnect_aresetn(interconnect_aresetn), //open + .peripheral_aresetn(peripheral_aresetn)); + + `include "parameter-defs.vh" + + wallypipelinedsoc #(P) + wallypipelinedsoc(.clk(CPUCLK), .reset_ext(bus_struct_reset), .reset(), + .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, + .HSELEXTSDC, .HCLK(HCLKOpen), .HRESETn(HRESETnOpen), + .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, + .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), + .GPIOIN, .GPIOOUT, .GPIOEN, + .UARTSin, .UARTSout, .SDCIntr); + + + // // wally + // // *** FIXME add sdc interrupt and HSELEXTSDC, remove old sdc + // wallypipelinedsocwrapper wallypipelinedsocwrapper + // (.clk(CPUCLK), + // .reset_ext(bus_struct_reset), + // // bus interface + // .HRDATAEXT(HRDATAEXT), + // .HREADYEXT(HREADYEXT), + // .HRESPEXT(HRESPEXT), + // .HSELEXT(HSELEXT), + // .HSELEXTSDC(HSELEXTSDC), + // .HCLK(HCLKOpen), // open + // .HRESETn(HRESETnOpen), // open + // .HADDR(HADDR), + // .HWDATA(HWDATA), + // .HWRITE(HWRITE), + // .HSIZE(HSIZE), + // .HBURST(HBURST), + // .HPROT(HPROT), + // .HTRANS(HTRANS), + // .HMASTLOCK(HMASTLOCK), + // .HREADY(HREADY), + // // GPIO + // .GPIOIN(GPIOIN), + // .GPIOOUT(GPIOOUT), + // .GPIOEN(GPIOEN), + // // UART + // .UARTSin(UARTSin), + // .UARTSout(UARTSout), + // .SDCIntr(SDCIntr) + // // SD Card + // /*.SDCDatIn(SDCDatIn), + // .SDCCmdIn(SDCCmdIn), + // .SDCCmdOut(SDCCmdOut), + // .SDCCmdOE(SDCCmdOE), + // .SDCCLK(SDCCLK));*/ + // ); + + // ahb lite to axi bridge + xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0 + (.s_ahb_hclk(CPUCLK), + .s_ahb_hresetn(peripheral_aresetn), + .s_ahb_hsel(HSELEXT | HSELEXTSDC), + .s_ahb_haddr(HADDR), + .s_ahb_hprot(HPROT), + .s_ahb_htrans(HTRANS), + .s_ahb_hsize(HSIZE), + .s_ahb_hwrite(HWRITE), + .s_ahb_hburst(HBURST), + .s_ahb_hwdata(HWDATA), + .s_ahb_hready_out(HREADYEXT), + .s_ahb_hready_in(HREADY), + .s_ahb_hrdata(HRDATAEXT), + .s_ahb_hresp(HRESPEXT), + .m_axi_awid(m_axi_awid), + .m_axi_awlen(m_axi_awlen), + .m_axi_awsize(m_axi_awsize), + .m_axi_awburst(m_axi_awburst), + .m_axi_awcache(m_axi_awcache), + .m_axi_awaddr(m_axi_awaddr), + .m_axi_awprot(m_axi_awprot), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_awready(m_axi_awready), + .m_axi_awlock(m_axi_awlock), + .m_axi_wdata(m_axi_wdata), + .m_axi_wstrb(m_axi_wstrb), + .m_axi_wlast(m_axi_wlast), + .m_axi_wvalid(m_axi_wvalid), + .m_axi_wready(m_axi_wready), + .m_axi_bid(m_axi_bid), + .m_axi_bresp(m_axi_bresp), + .m_axi_bvalid(m_axi_bvalid), + .m_axi_bready(m_axi_bready), + .m_axi_arid(m_axi_arid), + .m_axi_arlen(m_axi_arlen), + .m_axi_arsize(m_axi_arsize), + .m_axi_arburst(m_axi_arburst), + .m_axi_arprot(m_axi_arprot), + .m_axi_arcache(m_axi_arcache), + .m_axi_arvalid(m_axi_arvalid), + .m_axi_araddr(m_axi_araddr), + .m_axi_arlock(m_axi_arlock), + .m_axi_arready(m_axi_arready), + .m_axi_rid(m_axi_rid), + .m_axi_rdata(m_axi_rdata), + .m_axi_rresp(m_axi_rresp), + .m_axi_rvalid(m_axi_rvalid), + .m_axi_rlast(m_axi_rlast), + .m_axi_rready(m_axi_rready)); + + // AXI Crossbar for arbitrating the SDC and CPU -------------- + xlnx_axi_crossbar xlnx_axi_crossbar_0 + (.aclk(CPUCLK), + .aresetn(peripheral_aresetn), + + // Connect Masters + .s_axi_awid({4'b1000, m_axi_awid}), + .s_axi_awaddr({m01_axi_awaddr, m_axi_awaddr}), + .s_axi_awlen({m01_axi_awlen, m_axi_awlen}), + .s_axi_awsize({m01_axi_awsize, m_axi_awsize}), + .s_axi_awburst({m01_axi_awburst, m_axi_awburst}), + .s_axi_awlock({m01_axi_awlock, m_axi_awlock}), + .s_axi_awcache({m01_axi_awcache, m_axi_awcache}), + .s_axi_awprot({m01_axi_awprot, m_axi_awprot}), + .s_axi_awqos(8'b0), + .s_axi_awvalid({m01_axi_awvalid, m_axi_awvalid}), + .s_axi_awready({m01_axi_awready, m_axi_awready}), + .s_axi_wdata({m01_axi_wdata, m_axi_wdata}), + .s_axi_wstrb({m01_axi_wstrb, m_axi_wstrb}), + .s_axi_wlast({m01_axi_wlast, m_axi_wlast}), + .s_axi_wvalid({m01_axi_wvalid, m_axi_wvalid}), + .s_axi_wready({m01_axi_wready, m_axi_wready}), + .s_axi_bid({m01_axi_bid, m_axi_bid}), + .s_axi_bresp({m01_axi_bresp, m_axi_bresp}), + .s_axi_bvalid({m01_axi_bvalid, m_axi_bvalid}), + .s_axi_bready({m01_axi_bready, m_axi_bready}), + .s_axi_arid({4'b1000, m_axi_arid}), + .s_axi_araddr({m01_axi_araddr, m_axi_araddr}), + .s_axi_arlen({m01_axi_arlen, m_axi_arlen}), + .s_axi_arsize({m01_axi_arsize, m_axi_arsize}), + .s_axi_arburst({m01_axi_arburst, m_axi_arburst}), + .s_axi_arlock({m01_axi_arlock, m_axi_arlock}), + .s_axi_arcache({m01_axi_arcache, m_axi_arcache}), + .s_axi_arprot({m01_axi_arprot, m_axi_arprot}), + .s_axi_arqos(8'b0), + .s_axi_arvalid({m01_axi_arvalid, m_axi_arvalid}), + .s_axi_arready({m01_axi_arready, m_axi_arready}), + .s_axi_rid({m01_axi_rid, m_axi_rid}), + .s_axi_rdata({m01_axi_rdata, m_axi_rdata}), + .s_axi_rresp({m01_axi_rresp, m_axi_rresp}), + .s_axi_rlast({m01_axi_rlast, m_axi_rlast}), + .s_axi_rvalid({m01_axi_rvalid, m_axi_rvalid}), + .s_axi_rready({m01_axi_rready, m_axi_rready}), + + // Connect Slaves + .m_axi_awid({s01_axi_awid, s00_axi_awid}), + .m_axi_awlen({s01_axi_awlen, s00_axi_awlen}), + .m_axi_awsize({s01_axi_awsize, s00_axi_awsize}), + .m_axi_awburst({s01_axi_awburst, s00_axi_awburst}), + .m_axi_awcache({s01_axi_awcache, s00_axi_awcache}), + .m_axi_awaddr({s01_axi_awaddr, s00_axi_awaddr}), + .m_axi_awprot({s01_axi_awprot, s00_axi_awprot}), + .m_axi_awregion({s01_axi_awregion, s00_axi_awregion}), + .m_axi_awqos({s01_axi_awqos, s00_axi_awqos}), + .m_axi_awvalid({s01_axi_awvalid, s00_axi_awvalid}), + .m_axi_awready({s01_axi_awready, s00_axi_awready}), + .m_axi_awlock({s01_axi_awlock, s00_axi_awlock}), + .m_axi_wdata({s01_axi_wdata, s00_axi_wdata}), + .m_axi_wstrb({s01_axi_wstrb, s00_axi_wstrb}), + .m_axi_wlast({s01_axi_wlast, s00_axi_wlast}), + .m_axi_wvalid({s01_axi_wvalid, s00_axi_wvalid}), + .m_axi_wready({s01_axi_wready, s00_axi_wready}), + .m_axi_bid({4'b1000, s00_axi_bid}), + .m_axi_bresp({s01_axi_bresp, s00_axi_bresp}), + .m_axi_bvalid({s01_axi_bvalid, s00_axi_bvalid}), + .m_axi_bready({s01_axi_bready, s00_axi_bready}), + .m_axi_arid({s01_axi_arid, s00_axi_arid}), + .m_axi_arlen({s01_axi_arlen, s00_axi_arlen}), + .m_axi_arsize({s01_axi_arsize, s00_axi_arsize}), + .m_axi_arburst({s01_axi_arburst, s00_axi_arburst}), + .m_axi_arprot({s01_axi_arprot, s00_axi_arprot}), + .m_axi_arregion({s01_axi_arregion, s00_axi_arregion}), + .m_axi_arqos({s01_axi_arqos, s00_axi_arqos}), + .m_axi_arcache({s01_axi_arcache, s00_axi_arcache}), + .m_axi_arvalid({s01_axi_arvalid, s00_axi_arvalid}), + .m_axi_araddr({s01_axi_araddr, s00_axi_araddr}), + .m_axi_arlock({s01_axi_arlock, s00_axi_arlock}), + .m_axi_arready({s01_axi_arready, s00_axi_arready}), + .m_axi_rid({4'b1000, s00_axi_rid}), + .m_axi_rdata({s01_axi_rdata, s00_axi_rdata}), + .m_axi_rresp({s01_axi_rresp, s00_axi_rresp}), + .m_axi_rvalid({s01_axi_rvalid, s00_axi_rvalid}), + .m_axi_rlast({s01_axi_rlast, s00_axi_rlast}), + .m_axi_rready({s01_axi_rready, s00_axi_rready}) + ); + + // ----------------------------------------------------- + + // SDC Implementation ---------------------------------- + // + // The SDC peripheral from Eugene Tarassov takes in an AXI4Lite + // interface and outputs an AXI4 interface. In order to convert from + // one to the other, we use these dwidth converters to make sure the + // bit widths match the rest of the bus. + + xlnx_axi_dwidth_conv_64to32 axi_conv_down + (.s_axi_aclk(CPUCLK), + .s_axi_aresetn(peripheral_aresetn), + + // Slave interface + .s_axi_awaddr(s01_axi_awaddr), + .s_axi_awlen(s01_axi_awlen), + .s_axi_awsize(s01_axi_awsize), + .s_axi_awburst(s01_axi_awburst), + .s_axi_awlock(s01_axi_awlock), + .s_axi_awcache(s01_axi_awcache), + .s_axi_awprot(s01_axi_awprot), + .s_axi_awregion(s01_axi_awregion), + .s_axi_awqos(4'b0), + .s_axi_awvalid(s01_axi_awvalid), + .s_axi_awready(s01_axi_awready), + .s_axi_wdata(s01_axi_wdata), + .s_axi_wstrb(s01_axi_wstrb), + .s_axi_wlast(s01_axi_wlast), + .s_axi_wvalid(s01_axi_wvalid), + .s_axi_wready(s01_axi_wready), + .s_axi_bresp(s01_axi_bresp), + .s_axi_bvalid(s01_axi_bvalid), + .s_axi_bready(s01_axi_bready), + .s_axi_araddr(s01_axi_araddr), + .s_axi_arlen(s01_axi_arlen), + .s_axi_arsize(s01_axi_arsize), + .s_axi_arburst(s01_axi_arburst), + .s_axi_arlock(s01_axi_arlock), + .s_axi_arcache(s01_axi_arcache), + .s_axi_arprot(s01_axi_arprot), + .s_axi_arregion(s01_axi_arregion), + .s_axi_arqos(4'b0), + .s_axi_arvalid(s01_axi_arvalid), + .s_axi_arready(s01_axi_arready), + .s_axi_rdata(s01_axi_rdata), + .s_axi_rresp(s01_axi_rresp), + .s_axi_rlast(s01_axi_rlast), + .s_axi_rvalid(s01_axi_rvalid), + .s_axi_rready(s01_axi_rready), + + // Master interface + .m_axi_awaddr(axi4in_axi_awaddr), + .m_axi_awlen(axi4in_axi_awlen), + .m_axi_awsize(axi4in_axi_awsize), + .m_axi_awburst(axi4in_axi_awburst), + .m_axi_awlock(axi4in_axi_awlock), + .m_axi_awcache(axi4in_axi_awcache), + .m_axi_awprot(axi4in_axi_awprot), + .m_axi_awregion(axi4in_axi_awregion), + .m_axi_awqos(axi4in_axi_awqos), + .m_axi_awvalid(axi4in_axi_awvalid), + .m_axi_awready(axi4in_axi_awready), + .m_axi_wdata(axi4in_axi_wdata), + .m_axi_wstrb(axi4in_axi_wstrb), + .m_axi_wlast(axi4in_axi_wlast), + .m_axi_wvalid(axi4in_axi_wvalid), + .m_axi_wready(axi4in_axi_wready), + .m_axi_bresp(axi4in_axi_bresp), + .m_axi_bvalid(axi4in_axi_bvalid), + .m_axi_bready(axi4in_axi_bready), + .m_axi_araddr(axi4in_axi_araddr), + .m_axi_arlen(axi4in_axi_arlen), + .m_axi_arsize(axi4in_axi_arsize), + .m_axi_arburst(axi4in_axi_arburst), + .m_axi_arlock(axi4in_axi_arlock), + .m_axi_arcache(axi4in_axi_arcache), + .m_axi_arprot(axi4in_axi_arprot), + .m_axi_arregion(axi4in_axi_arregion), + .m_axi_arqos(axi4in_axi_arqos), + .m_axi_arvalid(axi4in_axi_arvalid), + .m_axi_arready(axi4in_axi_arready), + .m_axi_rdata(axi4in_axi_rdata), + .m_axi_rresp(axi4in_axi_rresp), + .m_axi_rlast(axi4in_axi_rlast), + .m_axi_rvalid(axi4in_axi_rvalid), + .m_axi_rready(axi4in_axi_rready) + ); + + xlnx_axi_prtcl_conv axi4tolite + (.aclk(CPUCLK), + .aresetn(peripheral_aresetn), + + // AXI4 In + .s_axi_awaddr(axi4in_axi_awaddr), + .s_axi_awlen(axi4in_axi_awlen), + .s_axi_awsize(axi4in_axi_awsize), + .s_axi_awburst(axi4in_axi_awburst), + .s_axi_awlock(axi4in_axi_awlock), + .s_axi_awcache(axi4in_axi_awcache), + .s_axi_awprot(axi4in_axi_awprot), + .s_axi_awregion(axi4in_axi_awregion), + .s_axi_awqos(axi4in_axi_awqos), + .s_axi_awvalid(axi4in_axi_awvalid), + .s_axi_awready(axi4in_axi_awready), + .s_axi_wdata(axi4in_axi_wdata), + .s_axi_wstrb(axi4in_axi_wstrb), + .s_axi_wlast(axi4in_axi_wlast), + .s_axi_wvalid(axi4in_axi_wvalid), + .s_axi_wready(axi4in_axi_wready), + .s_axi_bresp(axi4in_axi_bresp), + .s_axi_bvalid(axi4in_axi_bvalid), + .s_axi_bready(axi4in_axi_bready), + .s_axi_araddr(axi4in_axi_araddr), + .s_axi_arlen(axi4in_axi_arlen), + .s_axi_arsize(axi4in_axi_arsize), + .s_axi_arburst(axi4in_axi_arburst), + .s_axi_arlock(axi4in_axi_arlock), + .s_axi_arcache(axi4in_axi_arcache), + .s_axi_arprot(axi4in_axi_arprot), + .s_axi_arregion(axi4in_axi_arregion), + .s_axi_arqos(axi4in_axi_arqos), + .s_axi_arvalid(axi4in_axi_arvalid), + .s_axi_arready(axi4in_axi_arready), + .s_axi_rdata(axi4in_axi_rdata), + .s_axi_rresp(axi4in_axi_rresp), + .s_axi_rlast(axi4in_axi_rlast), + .s_axi_rvalid(axi4in_axi_rvalid), + .s_axi_rready(axi4in_axi_rready), + + // AXI4Lite Out + .m_axi_awaddr(SDCin_axi_awaddr), + .m_axi_awprot(SDCin_axi_awprot), + .m_axi_awvalid(SDCin_axi_awvalid), + .m_axi_awready(SDCin_axi_awready), + .m_axi_wdata(SDCin_axi_wdata), + .m_axi_wstrb(SDCin_axi_wstrb), + .m_axi_wvalid(SDCin_axi_wvalid), + .m_axi_wready(SDCin_axi_wready), + .m_axi_bresp(SDCin_axi_bresp), + .m_axi_bvalid(SDCin_axi_bvalid), + .m_axi_bready(SDCin_axi_bready), + .m_axi_araddr(SDCin_axi_araddr), + .m_axi_arprot(SDCin_axi_arprot), + .m_axi_arvalid(SDCin_axi_arvalid), + .m_axi_arready(SDCin_axi_arready), + .m_axi_rdata(SDCin_axi_rdata), + .m_axi_rresp(SDCin_axi_rresp), + .m_axi_rvalid(SDCin_axi_rvalid), + .m_axi_rready(SDCin_axi_rready) + + ); + + + sdc_controller axiSDC + (.clock(CPUCLK), + .async_resetn(peripheral_aresetn), + + // Slave Interface + .s_axi_awaddr({8'b0, SDCin_axi_awaddr[7:0]}), + .s_axi_awvalid(SDCin_axi_awvalid), + .s_axi_awready(SDCin_axi_awready), + .s_axi_wdata(SDCin_axi_wdata), + .s_axi_wvalid(SDCin_axi_wvalid), + .s_axi_wready(SDCin_axi_wready), + .s_axi_bresp(SDCin_axi_bresp), + .s_axi_bvalid(SDCin_axi_bvalid), + .s_axi_bready(SDCin_axi_bready), + .s_axi_araddr({8'b0, SDCin_axi_araddr[7:0]}), + .s_axi_arvalid(SDCin_axi_arvalid), + .s_axi_arready(SDCin_axi_arready), + .s_axi_rdata(SDCin_axi_rdata), + .s_axi_rresp(SDCin_axi_rresp), + .s_axi_rvalid(SDCin_axi_rvalid), + .s_axi_rready(SDCin_axi_rready), + + // Master Interface + .m_axi_awaddr(SDCout_axi_awaddr), + .m_axi_awlen(SDCout_axi_awlen), + .m_axi_awvalid(SDCout_axi_awvalid), + .m_axi_awready(SDCout_axi_awready), + .m_axi_wdata(SDCout_axi_wdata), + .m_axi_wlast(SDCout_axi_wlast), + .m_axi_wvalid(SDCout_axi_wvalid), + .m_axi_wready(SDCout_axi_wready), + .m_axi_bresp(SDCout_axi_bresp), + .m_axi_bvalid(SDCout_axi_bvalid), + .m_axi_bready(SDCout_axi_bready), + .m_axi_araddr(SDCout_axi_araddr), + .m_axi_arlen(SDCout_axi_arlen), + .m_axi_arvalid(SDCout_axi_arvalid), + .m_axi_arready(SDCout_axi_arready), + .m_axi_rdata(SDCout_axi_rdata), + .m_axi_rlast(SDCout_axi_rlast), + .m_axi_rresp(SDCout_axi_rresp), + .m_axi_rvalid(SDCout_axi_rvalid), + .m_axi_rready(SDCout_axi_rready), + + // SDC interface + //.sdio_cmd(1'b0), + //.sdio_dat(4'b0), + //.sdio_cd(1'b0) + + .sd_dat_reg_t(sd_dat_reg_t), + .sd_dat_reg_o(sd_dat_reg_o), + .sd_dat_i(sd_dat_i), + + .sd_cmd_reg_t(sd_cmd_reg_t), + .sd_cmd_reg_o(sd_cmd_reg_o), + .sd_cmd_i(sd_cmd_i), + + .sdio_clk(SDCCLK), + .sdio_cd(SDCCD), + + .interrupt(SDCIntr) + ); + + xlnx_axi_dwidth_conv_32to64 axi_conv_up + (.s_axi_aclk(CPUCLK), + .s_axi_aresetn(peripheral_aresetn), + + // Slave interface + .s_axi_awaddr(SDCout_axi_awaddr), + .s_axi_awlen(SDCout_axi_awlen), + .s_axi_awsize(3'b010), + .s_axi_awburst(2'b01), + .s_axi_awlock(1'b0), + .s_axi_awcache(4'b0), + .s_axi_awprot(3'b0), + .s_axi_awregion(4'b0), + .s_axi_awqos(4'b0), + .s_axi_awvalid(SDCout_axi_awvalid), + .s_axi_awready(SDCout_axi_awready), + .s_axi_wdata(SDCout_axi_wdata), + .s_axi_wstrb(8'b11111111), + .s_axi_wlast(SDCout_axi_wlast), + .s_axi_wvalid(SDCout_axi_wvalid), + .s_axi_wready(SDCout_axi_wready), + .s_axi_bresp(SDCout_axi_bresp), + .s_axi_bvalid(SDCout_axi_bvalid), + .s_axi_bready(SDCout_axi_bready), + .s_axi_araddr(SDCout_axi_araddr), + .s_axi_arlen(SDCout_axi_arlen), + .s_axi_arsize(3'b010), + .s_axi_arburst(2'b01), + .s_axi_arlock(1'b0), + .s_axi_arcache(4'b0), + .s_axi_arprot(3'b0), + .s_axi_arregion(4'b0), + .s_axi_arqos(4'b0), + .s_axi_arvalid(SDCout_axi_arvalid), + .s_axi_arready(SDCout_axi_arready), + .s_axi_rdata(SDCout_axi_rdata), + .s_axi_rresp(SDCout_axi_rresp), + .s_axi_rlast(SDCout_axi_rlast), + .s_axi_rvalid(SDCout_axi_rvalid), + .s_axi_rready(SDCout_axi_rready), + + // Master interface + .m_axi_awaddr(m01_axi_awaddr), + .m_axi_awlen(m01_axi_awlen), + .m_axi_awsize(m01_axi_awsize), + .m_axi_awburst(m01_axi_awburst), + .m_axi_awlock(m01_axi_awlock), + .m_axi_awcache(m01_axi_awcache), + .m_axi_awprot(m01_axi_awprot), + .m_axi_awregion(m01_axi_awregion), + .m_axi_awqos(m01_axi_awqos), + .m_axi_awvalid(m01_axi_awvalid), + .m_axi_awready(m01_axi_awready), + .m_axi_wdata(m01_axi_wdata), + .m_axi_wstrb(m01_axi_wstrb), + .m_axi_wlast(m01_axi_wlast), + .m_axi_wvalid(m01_axi_wvalid), + .m_axi_wready(m01_axi_wready), + .m_axi_bresp(m01_axi_bresp), + .m_axi_bvalid(m01_axi_bvalid), + .m_axi_bready(m01_axi_bready), + .m_axi_araddr(m01_axi_araddr), + .m_axi_arlen(m01_axi_arlen), + .m_axi_arsize(m01_axi_arsize), + .m_axi_arburst(m01_axi_arburst), + .m_axi_arlock(m01_axi_arlock), + .m_axi_arcache(m01_axi_arcache), + .m_axi_arprot(m01_axi_arprot), + .m_axi_arregion(m01_axi_arregion), + .m_axi_arqos(m01_axi_arqos), + .m_axi_arvalid(m01_axi_arvalid), + .m_axi_arready(m01_axi_arready), + .m_axi_rdata(m01_axi_rdata), + .m_axi_rresp(m01_axi_rresp), + .m_axi_rlast(m01_axi_rlast), + .m_axi_rvalid(m01_axi_rvalid), + .m_axi_rready(m01_axi_rready) + ); + + // End SDC signals -------------------------------------------- + + xlnx_axi_clock_converter xlnx_axi_clock_converter_0 + (.s_axi_aclk(CPUCLK), + .s_axi_aresetn(peripheral_aresetn), + .s_axi_awid(s00_axi_awid), + .s_axi_awlen(s00_axi_awlen), + .s_axi_awsize(s00_axi_awsize), + .s_axi_awburst(s00_axi_awburst), + .s_axi_awcache(s00_axi_awcache), + .s_axi_awaddr(s00_axi_awaddr[30:0] ), + .s_axi_awprot(s00_axi_awprot), + .s_axi_awregion(4'b0), // this could be a bug. bridge does not have these outputs + .s_axi_awqos(4'b0), // this could be a bug. bridge does not have these outputs + .s_axi_awvalid(s00_axi_awvalid), + .s_axi_awready(s00_axi_awready), + .s_axi_awlock(s00_axi_awlock), + .s_axi_wdata(s00_axi_wdata), + .s_axi_wstrb(s00_axi_wstrb), + .s_axi_wlast(s00_axi_wlast), + .s_axi_wvalid(s00_axi_wvalid), + .s_axi_wready(s00_axi_wready), + .s_axi_bid(s00_axi_bid), + .s_axi_bresp(s00_axi_bresp), + .s_axi_bvalid(s00_axi_bvalid), + .s_axi_bready(s00_axi_bready), + .s_axi_arid(s00_axi_arid), + .s_axi_arlen(s00_axi_arlen), + .s_axi_arsize(s00_axi_arsize), + .s_axi_arburst(s00_axi_arburst), + .s_axi_arprot(s00_axi_arprot), + .s_axi_arregion(4'b0), // this could be a bug. bridge does not have these outputs + .s_axi_arqos(4'b0), // this could be a bug. bridge does not have these outputs + .s_axi_arcache(s00_axi_arcache), + .s_axi_arvalid(s00_axi_arvalid), + .s_axi_araddr(s00_axi_araddr[30:0]), + .s_axi_arlock(s00_axi_arlock), + .s_axi_arready(s00_axi_arready), + .s_axi_rid(s00_axi_rid), + .s_axi_rdata(s00_axi_rdata), + .s_axi_rresp(s00_axi_rresp), + .s_axi_rvalid(s00_axi_rvalid), + .s_axi_rlast(s00_axi_rlast), + .s_axi_rready(s00_axi_rready), + + .m_axi_aclk(BUSCLK), + .m_axi_aresetn(~reset), + .m_axi_awid(BUS_axi_awid), + .m_axi_awlen(BUS_axi_awlen), + .m_axi_awsize(BUS_axi_awsize), + .m_axi_awburst(BUS_axi_awburst), + .m_axi_awcache(BUS_axi_awcache), + .m_axi_awaddr(BUS_axi_awaddr), + .m_axi_awprot(BUS_axi_awprot), + .m_axi_awregion(BUS_axi_awregion), + .m_axi_awqos(BUS_axi_awqos), + .m_axi_awvalid(BUS_axi_awvalid), + .m_axi_awready(BUS_axi_awready), + .m_axi_awlock(BUS_axi_awlock), + .m_axi_wdata(BUS_axi_wdata), + .m_axi_wstrb(BUS_axi_wstrb), + .m_axi_wlast(BUS_axi_wlast), + .m_axi_wvalid(BUS_axi_wvalid), + .m_axi_wready(BUS_axi_wready), + .m_axi_bid(BUS_axi_bid), + .m_axi_bresp(BUS_axi_bresp), + .m_axi_bvalid(BUS_axi_bvalid), + .m_axi_bready(BUS_axi_bready), + .m_axi_arid(BUS_axi_arid), + .m_axi_arlen(BUS_axi_arlen), + .m_axi_arsize(BUS_axi_arsize), + .m_axi_arburst(BUS_axi_arburst), + .m_axi_arprot(BUS_axi_arprot), + .m_axi_arregion(BUS_axi_arregion), + .m_axi_arqos(BUS_axi_arqos), + .m_axi_arcache(BUS_axi_arcache), + .m_axi_arvalid(BUS_axi_arvalid), + .m_axi_araddr(BUS_axi_araddr), + .m_axi_arlock(BUS_axi_arlock), + .m_axi_arready(BUS_axi_arready), + .m_axi_rid(BUS_axi_rid), + .m_axi_rdata(BUS_axi_rdata), + .m_axi_rresp(BUS_axi_rresp), + .m_axi_rvalid(BUS_axi_rvalid), + .m_axi_rlast(BUS_axi_rlast), + .m_axi_rready(BUS_axi_rready)); + + xlnx_ddr4 xlnx_ddr4_c0 + (.c0_init_calib_complete(c0_init_calib_complete), + .dbg_clk(dbg_clk), // open + .c0_sys_clk_p(default_250mhz_clk1_0_p), + .c0_sys_clk_n(default_250mhz_clk1_0_n), + .sys_rst(reset), + .dbg_bus(dbg_bus), // open + + // ddr4 I/O + .c0_ddr4_adr(c0_ddr4_adr), + .c0_ddr4_ba(c0_ddr4_ba), + .c0_ddr4_cke(c0_ddr4_cke), + .c0_ddr4_cs_n(c0_ddr4_cs_n), + .c0_ddr4_dm_dbi_n(c0_ddr4_dm_dbi_n), + .c0_ddr4_dq(c0_ddr4_dq), + .c0_ddr4_dqs_c(c0_ddr4_dqs_c), + .c0_ddr4_dqs_t(c0_ddr4_dqs_t), + .c0_ddr4_odt(c0_ddr4_odt), + .c0_ddr4_bg(c0_ddr4_bg), + .c0_ddr4_reset_n(c0_ddr4_reset_n), + .c0_ddr4_act_n(c0_ddr4_act_n), + .c0_ddr4_ck_c(c0_ddr4_ck_c), + .c0_ddr4_ck_t(c0_ddr4_ck_t), + .c0_ddr4_ui_clk(BUSCLK), + .c0_ddr4_ui_clk_sync_rst(c0_ddr4_ui_clk_sync_rst), + .c0_ddr4_aresetn(~reset), + + // axi + .c0_ddr4_s_axi_awid(BUS_axi_awid), + .c0_ddr4_s_axi_awaddr(BUS_axi_awaddr[30:0]), + .c0_ddr4_s_axi_awlen(BUS_axi_awlen), + .c0_ddr4_s_axi_awsize(BUS_axi_awsize), + .c0_ddr4_s_axi_awburst(BUS_axi_awburst), + .c0_ddr4_s_axi_awlock(BUS_axi_awlock), + .c0_ddr4_s_axi_awcache(BUS_axi_awcache), + .c0_ddr4_s_axi_awprot(BUS_axi_awprot), + .c0_ddr4_s_axi_awqos(BUS_axi_awqos), + .c0_ddr4_s_axi_awvalid(BUS_axi_awvalid), + .c0_ddr4_s_axi_awready(BUS_axi_awready), + .c0_ddr4_s_axi_wdata(BUS_axi_wdata), + .c0_ddr4_s_axi_wstrb(BUS_axi_wstrb), + .c0_ddr4_s_axi_wlast(BUS_axi_wlast), + .c0_ddr4_s_axi_wvalid(BUS_axi_wvalid), + .c0_ddr4_s_axi_wready(BUS_axi_wready), + .c0_ddr4_s_axi_bready(BUS_axi_bready), + .c0_ddr4_s_axi_bid(BUS_axi_bid), + .c0_ddr4_s_axi_bresp(BUS_axi_bresp), + .c0_ddr4_s_axi_bvalid(BUS_axi_bvalid), + .c0_ddr4_s_axi_arid(BUS_axi_arid), + .c0_ddr4_s_axi_araddr(BUS_axi_araddr[30:0]), + .c0_ddr4_s_axi_arlen(BUS_axi_arlen), + .c0_ddr4_s_axi_arsize(BUS_axi_arsize), + .c0_ddr4_s_axi_arburst(BUS_axi_arburst), + .c0_ddr4_s_axi_arlock(BUS_axi_arlock), + .c0_ddr4_s_axi_arcache(BUS_axi_arcache), + .c0_ddr4_s_axi_arprot(BUS_axi_arprot), + .c0_ddr4_s_axi_arqos(BUS_axi_arqos), + .c0_ddr4_s_axi_arvalid(BUS_axi_arvalid), + .c0_ddr4_s_axi_arready(BUS_axi_arready), + .c0_ddr4_s_axi_rready(BUS_axi_rready), + .c0_ddr4_s_axi_rlast(BUS_axi_rlast), + .c0_ddr4_s_axi_rvalid(BUS_axi_rvalid), + .c0_ddr4_s_axi_rresp(BUS_axi_rresp), + .c0_ddr4_s_axi_rid(BUS_axi_rid), + .c0_ddr4_s_axi_rdata(BUS_axi_rdata), + + .addn_ui_clkout1(CPUCLK), + .addn_ui_clkout2(CLK208)); + + + + +endmodule + From 3f7659c8ad2338e8cc5d4e7685ae13f9541386fa Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Thu, 30 May 2024 16:15:19 -0500 Subject: [PATCH 2/2] Removed old fpgaTop.v file. --- fpga/src/fpgaTop.v | 1114 -------------------------------------------- 1 file changed, 1114 deletions(-) delete mode 100644 fpga/src/fpgaTop.v diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v deleted file mode 100644 index 6038bb677..000000000 --- a/fpga/src/fpgaTop.v +++ /dev/null @@ -1,1114 +0,0 @@ -/////////////////////////////////////////// -// fpgaTop.sv -// -// Written: ross1728@gmail.com November 17, 2021 -// Modified: -// -// Purpose: This is a top level for the fpga's implementation of wally. -// Instantiates wallysoc, ddr4, abh lite to axi converters, pll, etc -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// - -module fpgaTop - (input default_250mhz_clk1_0_n, - input default_250mhz_clk1_0_p, - input reset, - input south_rst, - - input [3:0] GPI, - output [4:0] GPO, - - input UARTSin, - output UARTSout, - - inout [3:0] SDCDat, - output SDCCLK, - inout SDCCmd, - input SDCCD, - - output calib, - output cpu_reset, - output ahblite_resetn, - - output [16 : 0] c0_ddr4_adr, - output [1 : 0] c0_ddr4_ba, - output [0 : 0] c0_ddr4_cke, - output [0 : 0] c0_ddr4_cs_n, - inout [7 : 0] c0_ddr4_dm_dbi_n, - inout [63 : 0] c0_ddr4_dq, - inout [7 : 0] c0_ddr4_dqs_c, - inout [7 : 0] c0_ddr4_dqs_t, - output [0 : 0] c0_ddr4_odt, - output [0 : 0] c0_ddr4_bg, - output c0_ddr4_reset_n, - output c0_ddr4_act_n, - output [0 : 0] c0_ddr4_ck_c, - output [0 : 0] c0_ddr4_ck_t - ); - - wire CPUCLK; - wire c0_ddr4_ui_clk_sync_rst; - wire bus_struct_reset; - wire peripheral_reset; - wire interconnect_aresetn; - wire peripheral_aresetn; - wire mb_reset; - - wire HCLKOpen; - wire HRESETnOpen; - wire [64-1:0] HRDATAEXT; - wire HREADYEXT; - wire HRESPEXT; - (* mark_debug = "true" *) wire HSELEXT; - (* mark_debug = "true" *) wire HSELEXTSDC; // TEMP BOOT SIGNAL - JACOB - wire [31:0] HADDR; - wire [64-1:0] HWDATA; - wire HWRITE; - wire [2:0] HSIZE; - wire [2:0] HBURST; - wire [1:0] HTRANS; - wire HREADY; - wire [3:0] HPROT; - wire HMASTLOCK; - - - - wire [31:0] GPIOIN, GPIOOUT, GPIOEN; - - // Old SDC connections - // wire SDCCmdIn; - // wire SDCCmdOE; - // wire SDCCmdOut; - - (* mark_debug = "true" *)wire [3:0] m_axi_awid; - (* mark_debug = "true" *)wire [7:0] m_axi_awlen; - (* mark_debug = "true" *)wire [2:0] m_axi_awsize; - (* mark_debug = "true" *)wire [1:0] m_axi_awburst; - (* mark_debug = "true" *)wire [3:0] m_axi_awcache; - (* mark_debug = "true" *)wire [31:0] m_axi_awaddr; - (* mark_debug = "true" *)wire [2:0] m_axi_awprot; - (* mark_debug = "true" *)wire m_axi_awvalid; - (* mark_debug = "true" *)wire m_axi_awready; - (* mark_debug = "true" *)wire m_axi_awlock; - (* mark_debug = "true" *)wire [63:0] m_axi_wdata; - (* mark_debug = "true" *)wire [7:0] m_axi_wstrb; - (* mark_debug = "true" *)wire m_axi_wlast; - (* mark_debug = "true" *)wire m_axi_wvalid; - (* mark_debug = "true" *)wire m_axi_wready; - (* mark_debug = "true" *)wire [3:0] m_axi_bid; - (* mark_debug = "true" *)wire [1:0] m_axi_bresp; - (* mark_debug = "true" *)wire m_axi_bvalid; - (* mark_debug = "true" *)wire m_axi_bready; - (* mark_debug = "true" *)wire [3:0] m_axi_arid; - (* mark_debug = "true" *)wire [7:0] m_axi_arlen; - (* mark_debug = "true" *)wire [2:0] m_axi_arsize; - (* mark_debug = "true" *)wire [1:0] m_axi_arburst; - (* mark_debug = "true" *)wire [2:0] m_axi_arprot; - (* mark_debug = "true" *)wire [3:0] m_axi_arcache; - (* mark_debug = "true" *)wire m_axi_arvalid; - (* mark_debug = "true" *)wire [31:0] m_axi_araddr; - (* mark_debug = "true" *)wire m_axi_arlock; - (* mark_debug = "true" *)wire m_axi_arready; - (* mark_debug = "true" *)wire [3:0] m_axi_rid; - (* mark_debug = "true" *)wire [63:0] m_axi_rdata; - (* mark_debug = "true" *)wire [1:0] m_axi_rresp; - (* mark_debug = "true" *)wire m_axi_rvalid; - (* mark_debug = "true" *)wire m_axi_rlast; - (* mark_debug = "true" *)wire m_axi_rready; - - // Extra Bus signals - wire [3:0] BUS_axi_arregion; - wire [3:0] BUS_axi_arqos; - wire [3:0] BUS_axi_awregion; - wire [3:0] BUS_axi_awqos; - - // Bus signals - wire [3:0] BUS_axi_awid; - wire [7:0] BUS_axi_awlen; - wire [2:0] BUS_axi_awsize; - wire [1:0] BUS_axi_awburst; - wire [3:0] BUS_axi_awcache; - wire [30:0] BUS_axi_awaddr; - wire [2:0] BUS_axi_awprot; - wire BUS_axi_awvalid; - wire BUS_axi_awready; - wire BUS_axi_awlock; - wire [63:0] BUS_axi_wdata; - wire [7:0] BUS_axi_wstrb; - wire BUS_axi_wlast; - wire BUS_axi_wvalid; - wire BUS_axi_wready; - wire [3:0] BUS_axi_bid; - wire [1:0] BUS_axi_bresp; - wire BUS_axi_bvalid; - wire BUS_axi_bready; - wire [3:0] BUS_axi_arid; - wire [7:0] BUS_axi_arlen; - wire [2:0] BUS_axi_arsize; - wire [1:0] BUS_axi_arburst; - wire [2:0] BUS_axi_arprot; - wire [3:0] BUS_axi_arcache; - wire BUS_axi_arvalid; - wire [30:0] BUS_axi_araddr; - wire BUS_axi_arlock; - wire BUS_axi_arready; - wire [3:0] BUS_axi_rid; - wire [63:0] BUS_axi_rdata; - wire [1:0] BUS_axi_rresp; - wire BUS_axi_rvalid; - wire BUS_axi_rlast; - wire BUS_axi_rready; - - wire BUSCLK; - - - wire c0_init_calib_complete; - wire dbg_clk; - wire [511 : 0] dbg_bus; - - wire CLK208; - - - // Crossbar to Bus ------------------------------------------------ - - (* mark_debug = "true" *)wire s00_axi_aclk; - (* mark_debug = "true" *)wire s00_axi_aresetn; - (* mark_debug = "true" *)wire [3:0] s00_axi_awid; - (* mark_debug = "true" *)wire [31:0]s00_axi_awaddr; - (* mark_debug = "true" *)wire [7:0]s00_axi_awlen; - (* mark_debug = "true" *)wire [2:0]s00_axi_awsize; - (* mark_debug = "true" *)wire [1:0]s00_axi_awburst; - (* mark_debug = "true" *)wire [0:0]s00_axi_awlock; - (* mark_debug = "true" *)wire [3:0]s00_axi_awcache; - (* mark_debug = "true" *)wire [2:0]s00_axi_awprot; - (* mark_debug = "true" *)wire [3:0]s00_axi_awregion; - (* mark_debug = "true" *)wire [3:0]s00_axi_awqos; - (* mark_debug = "true" *) wire s00_axi_awvalid; - (* mark_debug = "true" *) wire s00_axi_awready; - (* mark_debug = "true" *)wire [63:0]s00_axi_wdata; - (* mark_debug = "true" *)wire [7:0]s00_axi_wstrb; - (* mark_debug = "true" *)wire s00_axi_wlast; - (* mark_debug = "true" *)wire s00_axi_wvalid; - (* mark_debug = "true" *)wire s00_axi_wready; - (* mark_debug = "true" *)wire [1:0]s00_axi_bresp; - (* mark_debug = "true" *)wire s00_axi_bvalid; - (* mark_debug = "true" *)wire s00_axi_bready; - (* mark_debug = "true" *)wire [31:0]s00_axi_araddr; - (* mark_debug = "true" *)wire [7:0]s00_axi_arlen; - (* mark_debug = "true" *)wire [2:0]s00_axi_arsize; - (* mark_debug = "true" *)wire [1:0]s00_axi_arburst; - (* mark_debug = "true" *)wire [0:0]s00_axi_arlock; - (* mark_debug = "true" *)wire [3:0]s00_axi_arcache; - (* mark_debug = "true" *)wire [2:0]s00_axi_arprot; - (* mark_debug = "true" *)wire [3:0]s00_axi_arregion; - (* mark_debug = "true" *)wire [3:0]s00_axi_arqos; - (* mark_debug = "true" *)wire s00_axi_arvalid; - (* mark_debug = "true" *)wire s00_axi_arready; - (* mark_debug = "true" *)wire [63:0]s00_axi_rdata; - (* mark_debug = "true" *)wire [1:0]s00_axi_rresp; - (* mark_debug = "true" *)wire s00_axi_rlast; - (* mark_debug = "true" *)wire s00_axi_rvalid; - (* mark_debug = "true" *)wire s00_axi_rready; - - (* mark_debug = "true" *)wire [3:0] s00_axi_bid; - (* mark_debug = "true" *)wire [3:0] s00_axi_rid; - - // 64to32 dwidth converter input interface------------------------- - wire s01_axi_aclk; - wire s01_axi_aresetn; - wire [3:0]s01_axi_awid; - wire [31:0]s01_axi_awaddr; - wire [7:0]s01_axi_awlen; - wire [2:0]s01_axi_awsize; - wire [1:0]s01_axi_awburst; - wire [0:0]s01_axi_awlock; - wire [3:0]s01_axi_awcache; - wire [2:0]s01_axi_awprot; - wire [3:0]s01_axi_awregion; - wire [3:0]s01_axi_awqos; // qos signals need to be 0 for SDC - (* mark_debug = "true" *) wire s01_axi_awvalid; - (* mark_debug = "true" *) wire s01_axi_awready; - wire [63:0]s01_axi_wdata; - wire [7:0]s01_axi_wstrb; - wire s01_axi_wlast; - wire s01_axi_wvalid; - wire s01_axi_wready; - wire [1:0]s01_axi_bresp; - wire s01_axi_bvalid; - wire s01_axi_bready; - wire [31:0]s01_axi_araddr; - wire [7:0]s01_axi_arlen; - wire [2:0]s01_axi_arsize; - wire [1:0]s01_axi_arburst; - wire [0:0]s01_axi_arlock; - wire [3:0]s01_axi_arcache; - wire [2:0]s01_axi_arprot; - wire [3:0]s01_axi_arregion; - wire [3:0]s01_axi_arqos; // - wire s01_axi_arvalid; - wire s01_axi_arready; - wire [63:0]s01_axi_rdata; - wire [1:0]s01_axi_rresp; - wire s01_axi_rlast; - wire s01_axi_rvalid; - wire s01_axi_rready; - - // Output Interface - wire [31:0]axi4in_axi_awaddr; - wire [7:0]axi4in_axi_awlen; - wire [2:0]axi4in_axi_awsize; - wire [1:0]axi4in_axi_awburst; - wire [0:0]axi4in_axi_awlock; - wire [3:0]axi4in_axi_awcache; - wire [2:0]axi4in_axi_awprot; - wire [3:0]axi4in_axi_awregion; - wire [3:0]axi4in_axi_awqos; - (* mark_debug = "true" *) wire axi4in_axi_awvalid; - (* mark_debug = "true" *) wire axi4in_axi_awready; - wire [31:0]axi4in_axi_wdata; - wire [3:0]axi4in_axi_wstrb; - wire axi4in_axi_wlast; - wire axi4in_axi_wvalid; - wire axi4in_axi_wready; - wire [1:0]axi4in_axi_bresp; - wire axi4in_axi_bvalid; - wire axi4in_axi_bready; - wire [31:0]axi4in_axi_araddr; - wire [7:0]axi4in_axi_arlen; - wire [2:0]axi4in_axi_arsize; - wire [1:0]axi4in_axi_arburst; - wire [0:0]axi4in_axi_arlock; - wire [3:0]axi4in_axi_arcache; - wire [2:0]axi4in_axi_arprot; - wire [3:0]axi4in_axi_arregion; - wire [3:0]axi4in_axi_arqos; - wire axi4in_axi_arvalid; - wire axi4in_axi_arready; - wire [31:0]axi4in_axi_rdata; - wire [1:0]axi4in_axi_rresp; - wire axi4in_axi_rlast; - wire axi4in_axi_rvalid; - wire axi4in_axi_rready; - - // AXI4 to AXI4-Lite Protocol converter output - (* mark_debug = "true" *) wire [31:0]SDCin_axi_awaddr; - (* mark_debug = "true" *) wire [2:0]SDCin_axi_awprot; - (* mark_debug = "true" *) wire SDCin_axi_awvalid; - (* mark_debug = "true" *) wire SDCin_axi_awready; - (* mark_debug = "true" *) wire [31:0]SDCin_axi_wdata; - (* mark_debug = "true" *) wire [3:0]SDCin_axi_wstrb; - (* mark_debug = "true" *) wire SDCin_axi_wvalid; - (* mark_debug = "true" *) wire SDCin_axi_wready; - (* mark_debug = "true" *) wire [1:0]SDCin_axi_bresp; - (* mark_debug = "true" *) wire SDCin_axi_bvalid; - (* mark_debug = "true" *) wire SDCin_axi_bready; - (* mark_debug = "true" *) wire [31:0]SDCin_axi_araddr; - (* mark_debug = "true" *) wire [2:0]SDCin_axi_arprot; - (* mark_debug = "true" *) wire SDCin_axi_arvalid; - (* mark_debug = "true" *) wire SDCin_axi_arready; - (* mark_debug = "true" *) wire [31:0]SDCin_axi_rdata; - (* mark_debug = "true" *) wire [1:0]SDCin_axi_rresp; - (* mark_debug = "true" *) wire SDCin_axi_rvalid; - (* mark_debug = "true" *) wire SDCin_axi_rready; - // ---------------------------------------------------------------- - - // 32to64 dwidth converter input interface ----------------------- - (* mark_debug = "true" *) wire [31:0]SDCout_axi_awaddr; - (* mark_debug = "true" *) wire [7:0]SDCout_axi_awlen; - wire [2:0]SDCout_axi_awsize; - wire [1:0]SDCout_axi_awburst; - wire [0:0]SDCout_axi_awlock; - wire [3:0]SDCout_axi_awcache; - wire [2:0]SDCout_axi_awprot; - wire [3:0]SDCout_axi_awregion; - wire [3:0]SDCout_axi_awqos; - (* mark_debug = "true" *) wire SDCout_axi_awvalid; - (* mark_debug = "true" *) wire SDCout_axi_awready; - (* mark_debug = "true" *) wire [31:0]SDCout_axi_wdata; - wire [3:0]SDCout_axi_wstrb; - (* mark_debug = "true" *) wire SDCout_axi_wlast; - (* mark_debug = "true" *) wire SDCout_axi_wvalid; - (* mark_debug = "true" *)wire SDCout_axi_wready; - (* mark_debug = "true" *) wire [1:0]SDCout_axi_bresp; - (* mark_debug = "true" *) wire SDCout_axi_bvalid; - (* mark_debug = "true" *) wire SDCout_axi_bready; - wire [31:0]SDCout_axi_araddr; - wire [7:0]SDCout_axi_arlen; - wire [2:0]SDCout_axi_arsize; - wire [1:0]SDCout_axi_arburst; - wire [0:0]SDCout_axi_arlock; - wire [3:0]SDCout_axi_arcache; - wire [2:0]SDCout_axi_arprot; - wire [3:0]SDCout_axi_arregion; - wire [3:0]SDCout_axi_arqos; - wire SDCout_axi_arvalid; - wire SDCout_axi_arready; - wire [31:0]SDCout_axi_rdata; - wire [1:0]SDCout_axi_rresp; - wire SDCout_axi_rlast; - wire SDCout_axi_rvalid; - wire SDCout_axi_rready; - - // Output Interface - (* mark_debug = "true" *) wire [3:0]m01_axi_awid; - (* mark_debug = "true" *) wire [31:0]m01_axi_awaddr; - (* mark_debug = "true" *) wire [7:0]m01_axi_awlen; - (* mark_debug = "true" *) wire [2:0]m01_axi_awsize; - (* mark_debug = "true" *) wire [1:0]m01_axi_awburst; - (* mark_debug = "true" *) wire [0:0]m01_axi_awlock; - (* mark_debug = "true" *) wire [3:0]m01_axi_awcache; - (* mark_debug = "true" *) wire [2:0]m01_axi_awprot; - (* mark_debug = "true" *) wire [3:0]m01_axi_awregion; - (* mark_debug = "true" *) wire [3:0]m01_axi_awqos; - (* mark_debug = "true" *) wire m01_axi_awvalid; - (* mark_debug = "true" *) wire m01_axi_awready; - (* mark_debug = "true" *) wire [63:0]m01_axi_wdata; - (* mark_debug = "true" *) wire [7:0]m01_axi_wstrb; - (* mark_debug = "true" *) wire m01_axi_wlast; - (* mark_debug = "true" *) wire m01_axi_wvalid; - (* mark_debug = "true" *) wire m01_axi_wready; - (* mark_debug = "true" *) wire [3:0] m01_axi_bid; - (* mark_debug = "true" *) wire [1:0]m01_axi_bresp; - (* mark_debug = "true" *) wire m01_axi_bvalid; - (* mark_debug = "true" *) wire m01_axi_bready; - (* mark_debug = "true" *) wire [3:0] m01_axi_arid; - (* mark_debug = "true" *) wire [31:0]m01_axi_araddr; - (* mark_debug = "true" *) wire [7:0]m01_axi_arlen; - (* mark_debug = "true" *) wire [2:0]m01_axi_arsize; - (* mark_debug = "true" *) wire [1:0]m01_axi_arburst; - (* mark_debug = "true" *) wire [0:0]m01_axi_arlock; - (* mark_debug = "true" *) wire [3:0]m01_axi_arcache; - (* mark_debug = "true" *) wire [2:0]m01_axi_arprot; - (* mark_debug = "true" *) wire [3:0]m01_axi_arregion; - (* mark_debug = "true" *) wire [3:0]m01_axi_arqos; - (* mark_debug = "true" *) wire m01_axi_arvalid; - (* mark_debug = "true" *) wire m01_axi_arready; - (* mark_debug = "true" *) wire [3:0] m01_axi_rid; - (* mark_debug = "true" *) wire [63:0]m01_axi_rdata; - (* mark_debug = "true" *) wire [1:0]m01_axi_rresp; - (* mark_debug = "true" *) wire m01_axi_rlast; - (* mark_debug = "true" *) wire m01_axi_rvalid; - (* mark_debug = "true" *) wire m01_axi_rready; - - // Old SDC input - // wire [3:0] SDCDatIn; - - // New SDC Command IOBUF connections - wire sd_cmd_i; - wire sd_cmd_reg_o; - wire sd_cmd_reg_t; - - // SD Card Interrupt signal - (* mark_debug = "true" *) wire SDCIntr; - - // New SDC Data IOBUF connections - wire [3:0] sd_dat_i; - wire [3:0] sd_dat_reg_o; - wire sd_dat_reg_t; - - assign GPIOIN = {28'b0, GPI}; - assign GPO = GPIOOUT[4:0]; - assign ahblite_resetn = peripheral_aresetn; - assign cpu_reset = bus_struct_reset; - assign calib = c0_init_calib_complete; - - - - // SD Card Tristate - /* - IOBUF iobufSDCMD(.T(~SDCCmdOE), // iobuf's T is active low - .I(SDCCmdOut), - .O(SDCCmdIn), - .IO(SDCCmd)); - - genvar i; - generate - for (i = 0; i < 4; i = i + 1) begin - IOBUF iobufSDCDat(.T(1'b1), - .I(1'b0), - .O(SDCDatIn[i]), - .IO(SDCDat[i])); - end - endgenerate - */ - - // IOBUFS for new SDC peripheral - IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(SDCCmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t)); - genvar i; - generate - for (i = 0; i < 4; i = i + 1) begin - IOBUF iobufSDCDat(.T(sd_dat_reg_t), - .I(sd_dat_reg_o[i]), - .O(sd_dat_i[i]), - .IO(SDCDat[i]) ); - end - endgenerate - - // IOBUF IOBUF_dat0 (.O(sd_dat_i[0]), .IO(sdio_dat[0]), .I(sd_dat_reg_o[0]), .T(sd_dat_reg_t)); - // IOBUF IOBUF_dat1 (.O(sd_dat_i[1]), .IO(sdio_dat[1]), .I(sd_dat_reg_o[1]), .T(sd_dat_reg_t)); - // IOBUF IOBUF_dat2 (.O(sd_dat_i[2]), .IO(sdio_dat[2]), .I(sd_dat_reg_o[2]), .T(sd_dat_reg_t)); - // IOBUF IOBUF_dat3 (.O(sd_dat_i[3]), .IO(sdio_dat[3]), .I(sd_dat_reg_o[3]), .T(sd_dat_reg_t)); - - - - // reset controller XILINX IP - xlnx_proc_sys_reset xlnx_proc_sys_reset_0 - (.slowest_sync_clk(CPUCLK), - .ext_reset_in(c0_ddr4_ui_clk_sync_rst), - .aux_reset_in(south_rst), - .mb_debug_sys_rst(1'b0), - .dcm_locked(c0_init_calib_complete), - .mb_reset(mb_reset), //open - .bus_struct_reset(bus_struct_reset), - .peripheral_reset(peripheral_reset), //open - .interconnect_aresetn(interconnect_aresetn), //open - .peripheral_aresetn(peripheral_aresetn)); - - - // wally - // *** FIXME add sdc interrupt and HSELEXTSDC, remove old sdc - wallypipelinedsocwrapper wallypipelinedsocwrapper - (.clk(CPUCLK), - .reset_ext(bus_struct_reset), - // bus interface - .HRDATAEXT(HRDATAEXT), - .HREADYEXT(HREADYEXT), - .HRESPEXT(HRESPEXT), - .HSELEXT(HSELEXT), - .HSELEXTSDC(HSELEXTSDC), - .HCLK(HCLKOpen), // open - .HRESETn(HRESETnOpen), // open - .HADDR(HADDR), - .HWDATA(HWDATA), - .HWRITE(HWRITE), - .HSIZE(HSIZE), - .HBURST(HBURST), - .HPROT(HPROT), - .HTRANS(HTRANS), - .HMASTLOCK(HMASTLOCK), - .HREADY(HREADY), - // GPIO - .GPIOIN(GPIOIN), - .GPIOOUT(GPIOOUT), - .GPIOEN(GPIOEN), - // UART - .UARTSin(UARTSin), - .UARTSout(UARTSout), - .SDCIntr(SDCIntr) - // SD Card - /*.SDCDatIn(SDCDatIn), - .SDCCmdIn(SDCCmdIn), - .SDCCmdOut(SDCCmdOut), - .SDCCmdOE(SDCCmdOE), - .SDCCLK(SDCCLK));*/ - ); - - // ahb lite to axi bridge - xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0 - (.s_ahb_hclk(CPUCLK), - .s_ahb_hresetn(peripheral_aresetn), - .s_ahb_hsel(HSELEXT | HSELEXTSDC), - .s_ahb_haddr(HADDR), - .s_ahb_hprot(HPROT), - .s_ahb_htrans(HTRANS), - .s_ahb_hsize(HSIZE), - .s_ahb_hwrite(HWRITE), - .s_ahb_hburst(HBURST), - .s_ahb_hwdata(HWDATA), - .s_ahb_hready_out(HREADYEXT), - .s_ahb_hready_in(HREADY), - .s_ahb_hrdata(HRDATAEXT), - .s_ahb_hresp(HRESPEXT), - .m_axi_awid(m_axi_awid), - .m_axi_awlen(m_axi_awlen), - .m_axi_awsize(m_axi_awsize), - .m_axi_awburst(m_axi_awburst), - .m_axi_awcache(m_axi_awcache), - .m_axi_awaddr(m_axi_awaddr), - .m_axi_awprot(m_axi_awprot), - .m_axi_awvalid(m_axi_awvalid), - .m_axi_awready(m_axi_awready), - .m_axi_awlock(m_axi_awlock), - .m_axi_wdata(m_axi_wdata), - .m_axi_wstrb(m_axi_wstrb), - .m_axi_wlast(m_axi_wlast), - .m_axi_wvalid(m_axi_wvalid), - .m_axi_wready(m_axi_wready), - .m_axi_bid(m_axi_bid), - .m_axi_bresp(m_axi_bresp), - .m_axi_bvalid(m_axi_bvalid), - .m_axi_bready(m_axi_bready), - .m_axi_arid(m_axi_arid), - .m_axi_arlen(m_axi_arlen), - .m_axi_arsize(m_axi_arsize), - .m_axi_arburst(m_axi_arburst), - .m_axi_arprot(m_axi_arprot), - .m_axi_arcache(m_axi_arcache), - .m_axi_arvalid(m_axi_arvalid), - .m_axi_araddr(m_axi_araddr), - .m_axi_arlock(m_axi_arlock), - .m_axi_arready(m_axi_arready), - .m_axi_rid(m_axi_rid), - .m_axi_rdata(m_axi_rdata), - .m_axi_rresp(m_axi_rresp), - .m_axi_rvalid(m_axi_rvalid), - .m_axi_rlast(m_axi_rlast), - .m_axi_rready(m_axi_rready)); - - // AXI Crossbar for arbitrating the SDC and CPU -------------- - xlnx_axi_crossbar xlnx_axi_crossbar_0 - (.aclk(CPUCLK), - .aresetn(peripheral_aresetn), - - // Connect Masters - .s_axi_awid({4'b1000, m_axi_awid}), - .s_axi_awaddr({m01_axi_awaddr, m_axi_awaddr}), - .s_axi_awlen({m01_axi_awlen, m_axi_awlen}), - .s_axi_awsize({m01_axi_awsize, m_axi_awsize}), - .s_axi_awburst({m01_axi_awburst, m_axi_awburst}), - .s_axi_awlock({m01_axi_awlock, m_axi_awlock}), - .s_axi_awcache({m01_axi_awcache, m_axi_awcache}), - .s_axi_awprot({m01_axi_awprot, m_axi_awprot}), - .s_axi_awqos(8'b0), - .s_axi_awvalid({m01_axi_awvalid, m_axi_awvalid}), - .s_axi_awready({m01_axi_awready, m_axi_awready}), - .s_axi_wdata({m01_axi_wdata, m_axi_wdata}), - .s_axi_wstrb({m01_axi_wstrb, m_axi_wstrb}), - .s_axi_wlast({m01_axi_wlast, m_axi_wlast}), - .s_axi_wvalid({m01_axi_wvalid, m_axi_wvalid}), - .s_axi_wready({m01_axi_wready, m_axi_wready}), - .s_axi_bid({m01_axi_bid, m_axi_bid}), - .s_axi_bresp({m01_axi_bresp, m_axi_bresp}), - .s_axi_bvalid({m01_axi_bvalid, m_axi_bvalid}), - .s_axi_bready({m01_axi_bready, m_axi_bready}), - .s_axi_arid({4'b1000, m_axi_arid}), - .s_axi_araddr({m01_axi_araddr, m_axi_araddr}), - .s_axi_arlen({m01_axi_arlen, m_axi_arlen}), - .s_axi_arsize({m01_axi_arsize, m_axi_arsize}), - .s_axi_arburst({m01_axi_arburst, m_axi_arburst}), - .s_axi_arlock({m01_axi_arlock, m_axi_arlock}), - .s_axi_arcache({m01_axi_arcache, m_axi_arcache}), - .s_axi_arprot({m01_axi_arprot, m_axi_arprot}), - .s_axi_arqos(8'b0), - .s_axi_arvalid({m01_axi_arvalid, m_axi_arvalid}), - .s_axi_arready({m01_axi_arready, m_axi_arready}), - .s_axi_rid({m01_axi_rid, m_axi_rid}), - .s_axi_rdata({m01_axi_rdata, m_axi_rdata}), - .s_axi_rresp({m01_axi_rresp, m_axi_rresp}), - .s_axi_rlast({m01_axi_rlast, m_axi_rlast}), - .s_axi_rvalid({m01_axi_rvalid, m_axi_rvalid}), - .s_axi_rready({m01_axi_rready, m_axi_rready}), - - // Connect Slaves - .m_axi_awid({s01_axi_awid, s00_axi_awid}), - .m_axi_awlen({s01_axi_awlen, s00_axi_awlen}), - .m_axi_awsize({s01_axi_awsize, s00_axi_awsize}), - .m_axi_awburst({s01_axi_awburst, s00_axi_awburst}), - .m_axi_awcache({s01_axi_awcache, s00_axi_awcache}), - .m_axi_awaddr({s01_axi_awaddr, s00_axi_awaddr}), - .m_axi_awprot({s01_axi_awprot, s00_axi_awprot}), - .m_axi_awregion({s01_axi_awregion, s00_axi_awregion}), - .m_axi_awqos({s01_axi_awqos, s00_axi_awqos}), - .m_axi_awvalid({s01_axi_awvalid, s00_axi_awvalid}), - .m_axi_awready({s01_axi_awready, s00_axi_awready}), - .m_axi_awlock({s01_axi_awlock, s00_axi_awlock}), - .m_axi_wdata({s01_axi_wdata, s00_axi_wdata}), - .m_axi_wstrb({s01_axi_wstrb, s00_axi_wstrb}), - .m_axi_wlast({s01_axi_wlast, s00_axi_wlast}), - .m_axi_wvalid({s01_axi_wvalid, s00_axi_wvalid}), - .m_axi_wready({s01_axi_wready, s00_axi_wready}), - .m_axi_bid({4'b1000, s00_axi_bid}), - .m_axi_bresp({s01_axi_bresp, s00_axi_bresp}), - .m_axi_bvalid({s01_axi_bvalid, s00_axi_bvalid}), - .m_axi_bready({s01_axi_bready, s00_axi_bready}), - .m_axi_arid({s01_axi_arid, s00_axi_arid}), - .m_axi_arlen({s01_axi_arlen, s00_axi_arlen}), - .m_axi_arsize({s01_axi_arsize, s00_axi_arsize}), - .m_axi_arburst({s01_axi_arburst, s00_axi_arburst}), - .m_axi_arprot({s01_axi_arprot, s00_axi_arprot}), - .m_axi_arregion({s01_axi_arregion, s00_axi_arregion}), - .m_axi_arqos({s01_axi_arqos, s00_axi_arqos}), - .m_axi_arcache({s01_axi_arcache, s00_axi_arcache}), - .m_axi_arvalid({s01_axi_arvalid, s00_axi_arvalid}), - .m_axi_araddr({s01_axi_araddr, s00_axi_araddr}), - .m_axi_arlock({s01_axi_arlock, s00_axi_arlock}), - .m_axi_arready({s01_axi_arready, s00_axi_arready}), - .m_axi_rid({4'b1000, s00_axi_rid}), - .m_axi_rdata({s01_axi_rdata, s00_axi_rdata}), - .m_axi_rresp({s01_axi_rresp, s00_axi_rresp}), - .m_axi_rvalid({s01_axi_rvalid, s00_axi_rvalid}), - .m_axi_rlast({s01_axi_rlast, s00_axi_rlast}), - .m_axi_rready({s01_axi_rready, s00_axi_rready}) - ); - - // ----------------------------------------------------- - - // SDC Implementation ---------------------------------- - // - // The SDC peripheral from Eugene Tarassov takes in an AXI4Lite - // interface and outputs an AXI4 interface. In order to convert from - // one to the other, we use these dwidth converters to make sure the - // bit widths match the rest of the bus. - - xlnx_axi_dwidth_conv_64to32 axi_conv_down - (.s_axi_aclk(CPUCLK), - .s_axi_aresetn(peripheral_aresetn), - - // Slave interface - .s_axi_awaddr(s01_axi_awaddr), - .s_axi_awlen(s01_axi_awlen), - .s_axi_awsize(s01_axi_awsize), - .s_axi_awburst(s01_axi_awburst), - .s_axi_awlock(s01_axi_awlock), - .s_axi_awcache(s01_axi_awcache), - .s_axi_awprot(s01_axi_awprot), - .s_axi_awregion(s01_axi_awregion), - .s_axi_awqos(4'b0), - .s_axi_awvalid(s01_axi_awvalid), - .s_axi_awready(s01_axi_awready), - .s_axi_wdata(s01_axi_wdata), - .s_axi_wstrb(s01_axi_wstrb), - .s_axi_wlast(s01_axi_wlast), - .s_axi_wvalid(s01_axi_wvalid), - .s_axi_wready(s01_axi_wready), - .s_axi_bresp(s01_axi_bresp), - .s_axi_bvalid(s01_axi_bvalid), - .s_axi_bready(s01_axi_bready), - .s_axi_araddr(s01_axi_araddr), - .s_axi_arlen(s01_axi_arlen), - .s_axi_arsize(s01_axi_arsize), - .s_axi_arburst(s01_axi_arburst), - .s_axi_arlock(s01_axi_arlock), - .s_axi_arcache(s01_axi_arcache), - .s_axi_arprot(s01_axi_arprot), - .s_axi_arregion(s01_axi_arregion), - .s_axi_arqos(4'b0), - .s_axi_arvalid(s01_axi_arvalid), - .s_axi_arready(s01_axi_arready), - .s_axi_rdata(s01_axi_rdata), - .s_axi_rresp(s01_axi_rresp), - .s_axi_rlast(s01_axi_rlast), - .s_axi_rvalid(s01_axi_rvalid), - .s_axi_rready(s01_axi_rready), - - // Master interface - .m_axi_awaddr(axi4in_axi_awaddr), - .m_axi_awlen(axi4in_axi_awlen), - .m_axi_awsize(axi4in_axi_awsize), - .m_axi_awburst(axi4in_axi_awburst), - .m_axi_awlock(axi4in_axi_awlock), - .m_axi_awcache(axi4in_axi_awcache), - .m_axi_awprot(axi4in_axi_awprot), - .m_axi_awregion(axi4in_axi_awregion), - .m_axi_awqos(axi4in_axi_awqos), - .m_axi_awvalid(axi4in_axi_awvalid), - .m_axi_awready(axi4in_axi_awready), - .m_axi_wdata(axi4in_axi_wdata), - .m_axi_wstrb(axi4in_axi_wstrb), - .m_axi_wlast(axi4in_axi_wlast), - .m_axi_wvalid(axi4in_axi_wvalid), - .m_axi_wready(axi4in_axi_wready), - .m_axi_bresp(axi4in_axi_bresp), - .m_axi_bvalid(axi4in_axi_bvalid), - .m_axi_bready(axi4in_axi_bready), - .m_axi_araddr(axi4in_axi_araddr), - .m_axi_arlen(axi4in_axi_arlen), - .m_axi_arsize(axi4in_axi_arsize), - .m_axi_arburst(axi4in_axi_arburst), - .m_axi_arlock(axi4in_axi_arlock), - .m_axi_arcache(axi4in_axi_arcache), - .m_axi_arprot(axi4in_axi_arprot), - .m_axi_arregion(axi4in_axi_arregion), - .m_axi_arqos(axi4in_axi_arqos), - .m_axi_arvalid(axi4in_axi_arvalid), - .m_axi_arready(axi4in_axi_arready), - .m_axi_rdata(axi4in_axi_rdata), - .m_axi_rresp(axi4in_axi_rresp), - .m_axi_rlast(axi4in_axi_rlast), - .m_axi_rvalid(axi4in_axi_rvalid), - .m_axi_rready(axi4in_axi_rready) - ); - - xlnx_axi_prtcl_conv axi4tolite - (.aclk(CPUCLK), - .aresetn(peripheral_aresetn), - - // AXI4 In - .s_axi_awaddr(axi4in_axi_awaddr), - .s_axi_awlen(axi4in_axi_awlen), - .s_axi_awsize(axi4in_axi_awsize), - .s_axi_awburst(axi4in_axi_awburst), - .s_axi_awlock(axi4in_axi_awlock), - .s_axi_awcache(axi4in_axi_awcache), - .s_axi_awprot(axi4in_axi_awprot), - .s_axi_awregion(axi4in_axi_awregion), - .s_axi_awqos(axi4in_axi_awqos), - .s_axi_awvalid(axi4in_axi_awvalid), - .s_axi_awready(axi4in_axi_awready), - .s_axi_wdata(axi4in_axi_wdata), - .s_axi_wstrb(axi4in_axi_wstrb), - .s_axi_wlast(axi4in_axi_wlast), - .s_axi_wvalid(axi4in_axi_wvalid), - .s_axi_wready(axi4in_axi_wready), - .s_axi_bresp(axi4in_axi_bresp), - .s_axi_bvalid(axi4in_axi_bvalid), - .s_axi_bready(axi4in_axi_bready), - .s_axi_araddr(axi4in_axi_araddr), - .s_axi_arlen(axi4in_axi_arlen), - .s_axi_arsize(axi4in_axi_arsize), - .s_axi_arburst(axi4in_axi_arburst), - .s_axi_arlock(axi4in_axi_arlock), - .s_axi_arcache(axi4in_axi_arcache), - .s_axi_arprot(axi4in_axi_arprot), - .s_axi_arregion(axi4in_axi_arregion), - .s_axi_arqos(axi4in_axi_arqos), - .s_axi_arvalid(axi4in_axi_arvalid), - .s_axi_arready(axi4in_axi_arready), - .s_axi_rdata(axi4in_axi_rdata), - .s_axi_rresp(axi4in_axi_rresp), - .s_axi_rlast(axi4in_axi_rlast), - .s_axi_rvalid(axi4in_axi_rvalid), - .s_axi_rready(axi4in_axi_rready), - - // AXI4Lite Out - .m_axi_awaddr(SDCin_axi_awaddr), - .m_axi_awprot(SDCin_axi_awprot), - .m_axi_awvalid(SDCin_axi_awvalid), - .m_axi_awready(SDCin_axi_awready), - .m_axi_wdata(SDCin_axi_wdata), - .m_axi_wstrb(SDCin_axi_wstrb), - .m_axi_wvalid(SDCin_axi_wvalid), - .m_axi_wready(SDCin_axi_wready), - .m_axi_bresp(SDCin_axi_bresp), - .m_axi_bvalid(SDCin_axi_bvalid), - .m_axi_bready(SDCin_axi_bready), - .m_axi_araddr(SDCin_axi_araddr), - .m_axi_arprot(SDCin_axi_arprot), - .m_axi_arvalid(SDCin_axi_arvalid), - .m_axi_arready(SDCin_axi_arready), - .m_axi_rdata(SDCin_axi_rdata), - .m_axi_rresp(SDCin_axi_rresp), - .m_axi_rvalid(SDCin_axi_rvalid), - .m_axi_rready(SDCin_axi_rready) - - ); - - - sdc_controller axiSDC - (.clock(CPUCLK), - .async_resetn(peripheral_aresetn), - - // Slave Interface - .s_axi_awaddr({8'b0, SDCin_axi_awaddr[7:0]}), - .s_axi_awvalid(SDCin_axi_awvalid), - .s_axi_awready(SDCin_axi_awready), - .s_axi_wdata(SDCin_axi_wdata), - .s_axi_wvalid(SDCin_axi_wvalid), - .s_axi_wready(SDCin_axi_wready), - .s_axi_bresp(SDCin_axi_bresp), - .s_axi_bvalid(SDCin_axi_bvalid), - .s_axi_bready(SDCin_axi_bready), - .s_axi_araddr({8'b0, SDCin_axi_araddr[7:0]}), - .s_axi_arvalid(SDCin_axi_arvalid), - .s_axi_arready(SDCin_axi_arready), - .s_axi_rdata(SDCin_axi_rdata), - .s_axi_rresp(SDCin_axi_rresp), - .s_axi_rvalid(SDCin_axi_rvalid), - .s_axi_rready(SDCin_axi_rready), - - // Master Interface - .m_axi_awaddr(SDCout_axi_awaddr), - .m_axi_awlen(SDCout_axi_awlen), - .m_axi_awvalid(SDCout_axi_awvalid), - .m_axi_awready(SDCout_axi_awready), - .m_axi_wdata(SDCout_axi_wdata), - .m_axi_wlast(SDCout_axi_wlast), - .m_axi_wvalid(SDCout_axi_wvalid), - .m_axi_wready(SDCout_axi_wready), - .m_axi_bresp(SDCout_axi_bresp), - .m_axi_bvalid(SDCout_axi_bvalid), - .m_axi_bready(SDCout_axi_bready), - .m_axi_araddr(SDCout_axi_araddr), - .m_axi_arlen(SDCout_axi_arlen), - .m_axi_arvalid(SDCout_axi_arvalid), - .m_axi_arready(SDCout_axi_arready), - .m_axi_rdata(SDCout_axi_rdata), - .m_axi_rlast(SDCout_axi_rlast), - .m_axi_rresp(SDCout_axi_rresp), - .m_axi_rvalid(SDCout_axi_rvalid), - .m_axi_rready(SDCout_axi_rready), - - // SDC interface - //.sdio_cmd(1'b0), - //.sdio_dat(4'b0), - //.sdio_cd(1'b0) - - .sd_dat_reg_t(sd_dat_reg_t), - .sd_dat_reg_o(sd_dat_reg_o), - .sd_dat_i(sd_dat_i), - - .sd_cmd_reg_t(sd_cmd_reg_t), - .sd_cmd_reg_o(sd_cmd_reg_o), - .sd_cmd_i(sd_cmd_i), - - .sdio_clk(SDCCLK), - .sdio_cd(SDCCD), - - .interrupt(SDCIntr) - ); - - xlnx_axi_dwidth_conv_32to64 axi_conv_up - (.s_axi_aclk(CPUCLK), - .s_axi_aresetn(peripheral_aresetn), - - // Slave interface - .s_axi_awaddr(SDCout_axi_awaddr), - .s_axi_awlen(SDCout_axi_awlen), - .s_axi_awsize(3'b010), - .s_axi_awburst(2'b01), - .s_axi_awlock(1'b0), - .s_axi_awcache(4'b0), - .s_axi_awprot(3'b0), - .s_axi_awregion(4'b0), - .s_axi_awqos(4'b0), - .s_axi_awvalid(SDCout_axi_awvalid), - .s_axi_awready(SDCout_axi_awready), - .s_axi_wdata(SDCout_axi_wdata), - .s_axi_wstrb(8'b11111111), - .s_axi_wlast(SDCout_axi_wlast), - .s_axi_wvalid(SDCout_axi_wvalid), - .s_axi_wready(SDCout_axi_wready), - .s_axi_bresp(SDCout_axi_bresp), - .s_axi_bvalid(SDCout_axi_bvalid), - .s_axi_bready(SDCout_axi_bready), - .s_axi_araddr(SDCout_axi_araddr), - .s_axi_arlen(SDCout_axi_arlen), - .s_axi_arsize(3'b010), - .s_axi_arburst(2'b01), - .s_axi_arlock(1'b0), - .s_axi_arcache(4'b0), - .s_axi_arprot(3'b0), - .s_axi_arregion(4'b0), - .s_axi_arqos(4'b0), - .s_axi_arvalid(SDCout_axi_arvalid), - .s_axi_arready(SDCout_axi_arready), - .s_axi_rdata(SDCout_axi_rdata), - .s_axi_rresp(SDCout_axi_rresp), - .s_axi_rlast(SDCout_axi_rlast), - .s_axi_rvalid(SDCout_axi_rvalid), - .s_axi_rready(SDCout_axi_rready), - - // Master interface - .m_axi_awaddr(m01_axi_awaddr), - .m_axi_awlen(m01_axi_awlen), - .m_axi_awsize(m01_axi_awsize), - .m_axi_awburst(m01_axi_awburst), - .m_axi_awlock(m01_axi_awlock), - .m_axi_awcache(m01_axi_awcache), - .m_axi_awprot(m01_axi_awprot), - .m_axi_awregion(m01_axi_awregion), - .m_axi_awqos(m01_axi_awqos), - .m_axi_awvalid(m01_axi_awvalid), - .m_axi_awready(m01_axi_awready), - .m_axi_wdata(m01_axi_wdata), - .m_axi_wstrb(m01_axi_wstrb), - .m_axi_wlast(m01_axi_wlast), - .m_axi_wvalid(m01_axi_wvalid), - .m_axi_wready(m01_axi_wready), - .m_axi_bresp(m01_axi_bresp), - .m_axi_bvalid(m01_axi_bvalid), - .m_axi_bready(m01_axi_bready), - .m_axi_araddr(m01_axi_araddr), - .m_axi_arlen(m01_axi_arlen), - .m_axi_arsize(m01_axi_arsize), - .m_axi_arburst(m01_axi_arburst), - .m_axi_arlock(m01_axi_arlock), - .m_axi_arcache(m01_axi_arcache), - .m_axi_arprot(m01_axi_arprot), - .m_axi_arregion(m01_axi_arregion), - .m_axi_arqos(m01_axi_arqos), - .m_axi_arvalid(m01_axi_arvalid), - .m_axi_arready(m01_axi_arready), - .m_axi_rdata(m01_axi_rdata), - .m_axi_rresp(m01_axi_rresp), - .m_axi_rlast(m01_axi_rlast), - .m_axi_rvalid(m01_axi_rvalid), - .m_axi_rready(m01_axi_rready) - ); - - // End SDC signals -------------------------------------------- - - xlnx_axi_clock_converter xlnx_axi_clock_converter_0 - (.s_axi_aclk(CPUCLK), - .s_axi_aresetn(peripheral_aresetn), - .s_axi_awid(s00_axi_awid), - .s_axi_awlen(s00_axi_awlen), - .s_axi_awsize(s00_axi_awsize), - .s_axi_awburst(s00_axi_awburst), - .s_axi_awcache(s00_axi_awcache), - .s_axi_awaddr(s00_axi_awaddr[30:0] ), - .s_axi_awprot(s00_axi_awprot), - .s_axi_awregion(4'b0), // this could be a bug. bridge does not have these outputs - .s_axi_awqos(4'b0), // this could be a bug. bridge does not have these outputs - .s_axi_awvalid(s00_axi_awvalid), - .s_axi_awready(s00_axi_awready), - .s_axi_awlock(s00_axi_awlock), - .s_axi_wdata(s00_axi_wdata), - .s_axi_wstrb(s00_axi_wstrb), - .s_axi_wlast(s00_axi_wlast), - .s_axi_wvalid(s00_axi_wvalid), - .s_axi_wready(s00_axi_wready), - .s_axi_bid(s00_axi_bid), - .s_axi_bresp(s00_axi_bresp), - .s_axi_bvalid(s00_axi_bvalid), - .s_axi_bready(s00_axi_bready), - .s_axi_arid(s00_axi_arid), - .s_axi_arlen(s00_axi_arlen), - .s_axi_arsize(s00_axi_arsize), - .s_axi_arburst(s00_axi_arburst), - .s_axi_arprot(s00_axi_arprot), - .s_axi_arregion(4'b0), // this could be a bug. bridge does not have these outputs - .s_axi_arqos(4'b0), // this could be a bug. bridge does not have these outputs - .s_axi_arcache(s00_axi_arcache), - .s_axi_arvalid(s00_axi_arvalid), - .s_axi_araddr(s00_axi_araddr[30:0]), - .s_axi_arlock(s00_axi_arlock), - .s_axi_arready(s00_axi_arready), - .s_axi_rid(s00_axi_rid), - .s_axi_rdata(s00_axi_rdata), - .s_axi_rresp(s00_axi_rresp), - .s_axi_rvalid(s00_axi_rvalid), - .s_axi_rlast(s00_axi_rlast), - .s_axi_rready(s00_axi_rready), - - .m_axi_aclk(BUSCLK), - .m_axi_aresetn(~reset), - .m_axi_awid(BUS_axi_awid), - .m_axi_awlen(BUS_axi_awlen), - .m_axi_awsize(BUS_axi_awsize), - .m_axi_awburst(BUS_axi_awburst), - .m_axi_awcache(BUS_axi_awcache), - .m_axi_awaddr(BUS_axi_awaddr), - .m_axi_awprot(BUS_axi_awprot), - .m_axi_awregion(BUS_axi_awregion), - .m_axi_awqos(BUS_axi_awqos), - .m_axi_awvalid(BUS_axi_awvalid), - .m_axi_awready(BUS_axi_awready), - .m_axi_awlock(BUS_axi_awlock), - .m_axi_wdata(BUS_axi_wdata), - .m_axi_wstrb(BUS_axi_wstrb), - .m_axi_wlast(BUS_axi_wlast), - .m_axi_wvalid(BUS_axi_wvalid), - .m_axi_wready(BUS_axi_wready), - .m_axi_bid(BUS_axi_bid), - .m_axi_bresp(BUS_axi_bresp), - .m_axi_bvalid(BUS_axi_bvalid), - .m_axi_bready(BUS_axi_bready), - .m_axi_arid(BUS_axi_arid), - .m_axi_arlen(BUS_axi_arlen), - .m_axi_arsize(BUS_axi_arsize), - .m_axi_arburst(BUS_axi_arburst), - .m_axi_arprot(BUS_axi_arprot), - .m_axi_arregion(BUS_axi_arregion), - .m_axi_arqos(BUS_axi_arqos), - .m_axi_arcache(BUS_axi_arcache), - .m_axi_arvalid(BUS_axi_arvalid), - .m_axi_araddr(BUS_axi_araddr), - .m_axi_arlock(BUS_axi_arlock), - .m_axi_arready(BUS_axi_arready), - .m_axi_rid(BUS_axi_rid), - .m_axi_rdata(BUS_axi_rdata), - .m_axi_rresp(BUS_axi_rresp), - .m_axi_rvalid(BUS_axi_rvalid), - .m_axi_rlast(BUS_axi_rlast), - .m_axi_rready(BUS_axi_rready)); - - xlnx_ddr4 xlnx_ddr4_c0 - (.c0_init_calib_complete(c0_init_calib_complete), - .dbg_clk(dbg_clk), // open - .c0_sys_clk_p(default_250mhz_clk1_0_p), - .c0_sys_clk_n(default_250mhz_clk1_0_n), - .sys_rst(reset), - .dbg_bus(dbg_bus), // open - - // ddr4 I/O - .c0_ddr4_adr(c0_ddr4_adr), - .c0_ddr4_ba(c0_ddr4_ba), - .c0_ddr4_cke(c0_ddr4_cke), - .c0_ddr4_cs_n(c0_ddr4_cs_n), - .c0_ddr4_dm_dbi_n(c0_ddr4_dm_dbi_n), - .c0_ddr4_dq(c0_ddr4_dq), - .c0_ddr4_dqs_c(c0_ddr4_dqs_c), - .c0_ddr4_dqs_t(c0_ddr4_dqs_t), - .c0_ddr4_odt(c0_ddr4_odt), - .c0_ddr4_bg(c0_ddr4_bg), - .c0_ddr4_reset_n(c0_ddr4_reset_n), - .c0_ddr4_act_n(c0_ddr4_act_n), - .c0_ddr4_ck_c(c0_ddr4_ck_c), - .c0_ddr4_ck_t(c0_ddr4_ck_t), - .c0_ddr4_ui_clk(BUSCLK), - .c0_ddr4_ui_clk_sync_rst(c0_ddr4_ui_clk_sync_rst), - .c0_ddr4_aresetn(~reset), - - // axi - .c0_ddr4_s_axi_awid(BUS_axi_awid), - .c0_ddr4_s_axi_awaddr(BUS_axi_awaddr[30:0]), - .c0_ddr4_s_axi_awlen(BUS_axi_awlen), - .c0_ddr4_s_axi_awsize(BUS_axi_awsize), - .c0_ddr4_s_axi_awburst(BUS_axi_awburst), - .c0_ddr4_s_axi_awlock(BUS_axi_awlock), - .c0_ddr4_s_axi_awcache(BUS_axi_awcache), - .c0_ddr4_s_axi_awprot(BUS_axi_awprot), - .c0_ddr4_s_axi_awqos(BUS_axi_awqos), - .c0_ddr4_s_axi_awvalid(BUS_axi_awvalid), - .c0_ddr4_s_axi_awready(BUS_axi_awready), - .c0_ddr4_s_axi_wdata(BUS_axi_wdata), - .c0_ddr4_s_axi_wstrb(BUS_axi_wstrb), - .c0_ddr4_s_axi_wlast(BUS_axi_wlast), - .c0_ddr4_s_axi_wvalid(BUS_axi_wvalid), - .c0_ddr4_s_axi_wready(BUS_axi_wready), - .c0_ddr4_s_axi_bready(BUS_axi_bready), - .c0_ddr4_s_axi_bid(BUS_axi_bid), - .c0_ddr4_s_axi_bresp(BUS_axi_bresp), - .c0_ddr4_s_axi_bvalid(BUS_axi_bvalid), - .c0_ddr4_s_axi_arid(BUS_axi_arid), - .c0_ddr4_s_axi_araddr(BUS_axi_araddr[30:0]), - .c0_ddr4_s_axi_arlen(BUS_axi_arlen), - .c0_ddr4_s_axi_arsize(BUS_axi_arsize), - .c0_ddr4_s_axi_arburst(BUS_axi_arburst), - .c0_ddr4_s_axi_arlock(BUS_axi_arlock), - .c0_ddr4_s_axi_arcache(BUS_axi_arcache), - .c0_ddr4_s_axi_arprot(BUS_axi_arprot), - .c0_ddr4_s_axi_arqos(BUS_axi_arqos), - .c0_ddr4_s_axi_arvalid(BUS_axi_arvalid), - .c0_ddr4_s_axi_arready(BUS_axi_arready), - .c0_ddr4_s_axi_rready(BUS_axi_rready), - .c0_ddr4_s_axi_rlast(BUS_axi_rlast), - .c0_ddr4_s_axi_rvalid(BUS_axi_rvalid), - .c0_ddr4_s_axi_rresp(BUS_axi_rresp), - .c0_ddr4_s_axi_rid(BUS_axi_rid), - .c0_ddr4_s_axi_rdata(BUS_axi_rdata), - - .addn_ui_clkout1(CPUCLK), - .addn_ui_clkout2(CLK208)); - - - - -endmodule -