From 657e19df08576aef2b3d64ada31c7918d194d2fe Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Sat, 17 Sep 2022 23:14:28 +0000 Subject: [PATCH 1/6] added full coverage of subword loads and stores to endianness test --- .../WALLY-endianness-01.reference_output | 74 +++++--- .../privilege/src/WALLY-endianness-01.S | 158 +++++++++++++++--- 2 files changed, 193 insertions(+), 39 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-endianness-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-endianness-01.reference_output index 54d95300d..e1984a7cb 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-endianness-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-endianness-01.reference_output @@ -1,26 +1,62 @@ -00000011 # Test *** NUMBER: Read of 1st byte of 0xAABBCCDDEEFF1122 in M mode little endian +eeff1122 # Test *** Number: M mode little endian load/store double of 0xaabbccddeeff1122 +aabbccdd # NOTE: since we're doing a store that matches the width of the load, we cut out all the sign extension +eeff1122 # M mode little endian load/store word of 0xaabbccddeeff1122 +deadbeef # NOTE: the memory was already filled with deadbeef's so subword overwrite some, but not all of them. this is why the values are filled with deadbeefs, rather than 00's or ff's +dead1122 # M mode little endian load/store halfword of 0xaabbccddeeff1122 +deadbeef +deadbe22 # M mode little endian load/store byte of 0xaabbccddeeff1122 +deadbeef +ddccbbaa # M mode big endian load/store double of 0x2211ffeeddccbbaa +2211ffee +ddccbbaa # M mode big endian load/store word of 0x2211ffeeddccbbaa +deadbeef +deadbbaa # M mode big endian load/store halfword of 0x2211ffeeddccbbaa +deadbeef +deadbeaa # M mode big endian load/store byte of 0x2211ffeeddccbbaa +deadbeef +0000000b # ecall after going from M mode to S mode 00000000 -ffffffff # sign extended value after Read of 1st byte of 0xAABBCCDDEEFF1122 in M mode big endian -bbffffff # This is 0xbb sign extended and stored in big endian mode -0000000b # mcause from ecall going from M mode to S mode +eeff1122 # S mode little endian load/store double of 0xaabbccddeeff1122 +aabbccdd +eeff1122 # S mode little endian load/store word of 0xaabbccddeeff1122 +deadbeef +dead1122 # S mode little endian load/store halfword of 0xaabbccddeeff1122 +deadbeef +deadbe22 # S mode little endian load/store byte of 0xaabbccddeeff1122 +deadbeef +00000009 # ecall after going from S mode to M mode 00000000 -00000011 # Read of 1st byte of 0xAABBCCDDEEFF1122 in S mode little endian +0000000b # ecall after going from M mode to S mode 00000000 -00000009 # mcause from ecall going from S mode to M mode (necessary to change mstatus bits) +ddccbbaa # S mode big endian load/store double of 0x2211ffeeddccbbaa +2211ffee +ddccbbaa # S mode big endian load/store word of 0x2211ffeeddccbbaa +deadbeef +deadbbaa # S mode big endian load/store halfword of 0x2211ffeeddccbbaa +deadbeef +deadbeaa # S mode big endian load/store byte of 0x2211ffeeddccbbaa +deadbeef +00000009 # ecall after going from S mode to U mode 00000000 -0000000b # mcause from ecall going back from M mode to S mode -00000000 -ffffffff # sign extended value after Read of 1st byte of 0xAABBCCDDEEFF1122 in S mode big endian -bbffffff # This is 0xbb sign extended and stored in big endian mode -00000009 # mcause from ecall going from S mode to U mode +eeff1122 # U mode little endian load/store double of 0xaabbccddeeff1122 +aabbccdd +eeff1122 # U mode little endian load/store word of 0xaabbccddeeff1122 +deadbeef +dead1122 # U mode little endian load/store halfword of 0xaabbccddeeff1122 +deadbeef +deadbe22 # U mode little endian load/store byte of 0xaabbccddeeff1122 +deadbeef +00000008 # ecall after going from U mode to M mode 00000000 -00000011 # Read of 1st byte of 0xAABBCCDDEEFF1122 in U mode little endian +0000000b # ecall after going from M mode to U mode 00000000 -00000008 # mcause from ecall going from U mode to M mode (necessary to change mstatus bits) +ddccbbaa # U mode big endian load/store double of 0x2211ffeeddccbbaa +2211ffee +ddccbbaa # U mode big endian load/store word of 0x2211ffeeddccbbaa +deadbeef +deadbbaa # U mode big endian load/store halfword of 0x2211ffeeddccbbaa +deadbeef +deadbeaa # U mode big endian load/store byte of 0x2211ffeeddccbbaa +deadbeef +00000008 # ecall after ending tests in U mode 00000000 -0000000b # mcause from ecall going back from M mode to U mode -00000000 -ffffffff # sign extended value after Read of 1st byte of 0xAABBCCDDEEFF1122 in U mode big endian -bbffffff # This is 0xbb sign extended and stored in big endian mode -00000008 # Ecall from terminating tests in U mode. -00000000 \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-endianness-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-endianness-01.S index 77e2ab8ec..f3fe822b8 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-endianness-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-endianness-01.S @@ -34,25 +34,62 @@ TRAP_HANDLER m // correctly with the relevant status bit indicating endianness for each mode. // do this by going to each mode with and testing loads with the big endian bit on and off work correctly -// *** It appears has the MBE, SBE, and UBE bits of mstatus hardwired to zero +// *** It appears Sail has the MBE, SBE, and UBE bits of mstatus hardwired to zero + +// M Mode little Endianness tests: li x28, 0xAABBCCDDEEFF1122 li x29, 0x8000F000 -sd x28, 0(x29) // Store test value into memory address in little endian mode -// in little endian mode, byte at 0x1(x29) is 0x11 -// in big endian mode, 0x1(x29) should be 0xBB +sd x28, 0(x29) // value stored in memory as 0xAABBCCDDEEFF1122 -lb x30, 0x1(x29) // Test M Mode Little endianness, should return 0x11 -sd x30, 0(t1) // store recorded M mode Little endian value to output +ld x30, 0(x29) // test load double, should read out 0xAABBCCDDEEFF1122 +sd x30, 0(t1) // test store double, should save 0xAABBCCDDEEFF1122 +addi t1, t1, 8 +addi a6, a6, 8 + +lw x30, 0(x29) // test load word, should read out 0xEEFF1122 +sw x30, 0(t1) // test store word, should save 0xEEFF1122 +addi t1, t1, 8 +addi a6, a6, 8 + +lh x30, 0(x29) // test load half, should read out 0x1122 +sh x30, 0(t1) // test store half, should save 0x1122 +addi t1, t1, 8 +addi a6, a6, 8 + +lb x30, 0(x29) // test load byte, should read out 0x22 +sb x30, 0(t1) // test store byte, should save 0x22 addi t1, t1, 8 addi a6, a6, 8 li x28, 0x2000000000 csrs mstatus, x28 // turn on big endianness for M mode -lb x30, 0x1(x29) // Test M mode big endaianness, should return 0xBB -sd x30, 0(t1) // store recorded M mode big endian value to output -addi t1, t1, 8 +// M mode Big Endianness tests +// In big endian modes, all values are sign extended to the right, rather than left + +li x28, 0xAABBCCDDEEFF1122 +li x29, 0x8000F000 +sd x28, 0(x29) // value stored in memory as 0x2211FFEECCDDBBAA + +ld x30, 0(x29) // test load double, should read out 0xAABBCCDDEEFF1122 +sd x30, 0(t1) // test store double, should save 0x2211FFEEDDCCBBAA +addi t1, t1, 8 +addi a6, a6, 8 + +lw x30, 0(x29) // test load word, should read out 0xAABBCCDD +sw x30, 0(t1) // test store word, should save 0xDDCCBBAA +addi t1, t1, 8 +addi a6, a6, 8 + +lh x30, 0(x29) // test load half, should read out 0xAABB +sh x30, 0(t1) // test store half, should save 0xBBAA +addi t1, t1, 8 +addi a6, a6, 8 + +lb x30, 0(x29) // test load byte, should read out 0xAA +sb x30, 0(t1) // test store byte, should save 0xAA +addi t1, t1, 8 addi a6, a6, 8 li x28, 0x2000000000 @@ -60,8 +97,29 @@ csrc mstatus, x28 // Turn off big endianness for M mode before going into the tr GOTO_S_MODE -lb x30, 0x1(x29) // Test S Mode Little endianness, should return 0x11 -sd x30, 0(t1) // store recorded M mode Little endian value to output +// S mode Little endian tests + +li x28, 0xAABBCCDDEEFF1122 +li x29, 0x8000F000 +sd x28, 0(x29) // value stored in memory as 0xAABBCCDDEEFF1122 + +ld x30, 0(x29) // test load double, should read out 0xAABBCCDDEEFF1122 +sd x30, 0(t1) // test store double, should save 0xAABBCCDDEEFF1122 +addi t1, t1, 8 +addi a6, a6, 8 + +lw x30, 0(x29) // test load word, should read out 0xEEFF1122 +sw x30, 0(t1) // test store word, should save 0xEEFF1122 +addi t1, t1, 8 +addi a6, a6, 8 + +lh x30, 0(x29) // test load half, should read out 0x1122 +sh x30, 0(t1) // test store half, should save 0x1122 +addi t1, t1, 8 +addi a6, a6, 8 + +lb x30, 0(x29) // test load byte, should read out 0x22 +sb x30, 0(t1) // test store byte, should save 0x22 addi t1, t1, 8 addi a6, a6, 8 @@ -72,18 +130,57 @@ csrs mstatus, x28 // turn on big endianness for S mode GOTO_S_MODE -lb x30, 0x1(x29) // Test S mode big endaianness, should return 0xBB -sd x30, 0(t1) // store recorded S mode big endian value to output -addi t1, t1, 8 +// S mode Big endian tests + +li x28, 0xAABBCCDDEEFF1122 +li x29, 0x8000F000 +sd x28, 0(x29) // value stored in memory as 0x2211FFEECCDDBBAA + +ld x30, 0(x29) // test load double, should read out 0xAABBCCDDEEFF1122 +sd x30, 0(t1) // test store double, should save 0x2211FFEEDDCCBBAA +addi t1, t1, 8 addi a6, a6, 8 -# li x28, 0x1000000000 -# csrc sstatus, x28 // Turn off big endianness for S mode before going into the trap handler +lw x30, 0(x29) // test load word, should read out 0xAABBCCDD +sw x30, 0(t1) // test store word, should save 0xDDCCBBAA +addi t1, t1, 8 +addi a6, a6, 8 + +lh x30, 0(x29) // test load half, should read out 0xAABB +sh x30, 0(t1) // test store half, should save 0xBBAA +addi t1, t1, 8 +addi a6, a6, 8 + +lb x30, 0(x29) // test load byte, should read out 0xAA +sb x30, 0(t1) // test store byte, should save 0xAA +addi t1, t1, 8 +addi a6, a6, 8 GOTO_U_MODE -lb x30, 0x1(x29) // Test U Mode Little endianness, should return 0x11 -sd x30, 0(t1) // store recorded M mode Little endian value to output +// U mode Little endian tests + +li x28, 0xAABBCCDDEEFF1122 +li x29, 0x8000F000 +sd x28, 0(x29) // value stored in memory as 0xAABBCCDDEEFF1122 + +ld x30, 0(x29) // test load double, should read out 0xAABBCCDDEEFF1122 +sd x30, 0(t1) // test store double, should save 0xAABBCCDDEEFF1122 +addi t1, t1, 8 +addi a6, a6, 8 + +lw x30, 0(x29) // test load word, should read out 0xEEFF1122 +sw x30, 0(t1) // test store word, should save 0xEEFF1122 +addi t1, t1, 8 +addi a6, a6, 8 + +lh x30, 0(x29) // test load half, should read out 0x1122 +sh x30, 0(t1) // test store half, should save 0x1122 +addi t1, t1, 8 +addi a6, a6, 8 + +lb x30, 0(x29) // test load byte, should read out 0x22 +sb x30, 0(t1) // test store byte, should save 0x22 addi t1, t1, 8 addi a6, a6, 8 @@ -94,8 +191,29 @@ csrs mstatus, x28 // turn on big endianness for U mode GOTO_U_MODE -lb x30, 0x1(x29) // Test U mode big endaianness, should return 0xBB -sd x30, 0(t1) // store recorded U mode big endian value to output +// U mode Big endian tests + +li x28, 0xAABBCCDDEEFF1122 +li x29, 0x8000F000 +sd x28, 0(x29) // value stored in memory as 0x2211FFEECCDDBBAA + +ld x30, 0(x29) // test load double, should read out 0xAABBCCDDEEFF1122 +sd x30, 0(t1) // test store double, should save 0x2211FFEEDDCCBBAA +addi t1, t1, 8 +addi a6, a6, 8 + +lw x30, 0(x29) // test load word, should read out 0xAABBCCDD +sw x30, 0(t1) // test store word, should save 0xDDCCBBAA +addi t1, t1, 8 +addi a6, a6, 8 + +lh x30, 0(x29) // test load half, should read out 0xAABB +sh x30, 0(t1) // test store half, should save 0xBBAA +addi t1, t1, 8 +addi a6, a6, 8 + +lb x30, 0(x29) // test load byte, should read out 0xAA +sb x30, 0(t1) // test store byte, should save 0xAA addi t1, t1, 8 addi a6, a6, 8 From 99596fac840b32147484522eabc45c588f285056 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Sun, 18 Sep 2022 00:09:52 +0000 Subject: [PATCH 2/6] Fixed typos in existing endianness test --- .../references/WALLY-endianness-01.reference_output | 2 +- .../rv64i_m/privilege/src/WALLY-endianness-01.S | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-endianness-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-endianness-01.reference_output index e1984a7cb..349a2bca3 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-endianness-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-endianness-01.reference_output @@ -1,4 +1,4 @@ -eeff1122 # Test *** Number: M mode little endian load/store double of 0xaabbccddeeff1122 +eeff1122 # Test 5.3.2.4: M mode little endian load/store double of 0xaabbccddeeff1122 aabbccdd # NOTE: since we're doing a store that matches the width of the load, we cut out all the sign extension eeff1122 # M mode little endian load/store word of 0xaabbccddeeff1122 deadbeef # NOTE: the memory was already filled with deadbeef's so subword overwrite some, but not all of them. this is why the values are filled with deadbeefs, rather than 00's or ff's diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-endianness-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-endianness-01.S index f3fe822b8..38bc6fd18 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-endianness-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-endianness-01.S @@ -30,7 +30,7 @@ INIT_TESTS TRAP_HANDLER m -// Test ***Number: testing that accesses to sub-word memory acceses not on a word boundary go +// Test 5.3.2.4: testing that accesses to sub-word memory acceses not on a word boundary go // correctly with the relevant status bit indicating endianness for each mode. // do this by going to each mode with and testing loads with the big endian bit on and off work correctly @@ -70,7 +70,7 @@ csrs mstatus, x28 // turn on big endianness for M mode li x28, 0xAABBCCDDEEFF1122 li x29, 0x8000F000 -sd x28, 0(x29) // value stored in memory as 0x2211FFEECCDDBBAA +sd x28, 0(x29) // value stored in memory as 0x2211FFEEDDCCBBAA ld x30, 0(x29) // test load double, should read out 0xAABBCCDDEEFF1122 sd x30, 0(t1) // test store double, should save 0x2211FFEEDDCCBBAA @@ -134,7 +134,7 @@ GOTO_S_MODE li x28, 0xAABBCCDDEEFF1122 li x29, 0x8000F000 -sd x28, 0(x29) // value stored in memory as 0x2211FFEECCDDBBAA +sd x28, 0(x29) // value stored in memory as 0x2211FFEEDDCCBBAA ld x30, 0(x29) // test load double, should read out 0xAABBCCDDEEFF1122 sd x30, 0(t1) // test store double, should save 0x2211FFEEDDCCBBAA @@ -195,7 +195,7 @@ GOTO_U_MODE li x28, 0xAABBCCDDEEFF1122 li x29, 0x8000F000 -sd x28, 0(x29) // value stored in memory as 0x2211FFEECCDDBBAA +sd x28, 0(x29) // value stored in memory as 0x2211FFEEDDCCBBAA ld x30, 0(x29) // test load double, should read out 0xAABBCCDDEEFF1122 sd x30, 0(t1) // test store double, should save 0x2211FFEEDDCCBBAA From dda3b2d38327e39f9162826d3af6d86833d8edf6 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Sun, 18 Sep 2022 00:10:29 +0000 Subject: [PATCH 3/6] ported endianness tests to 32 bits (not tested in regression yet) --- .../WALLY-endianness-01.reference_output | 25 +++ .../privilege/src/WALLY-endianness-01.S | 192 ++++++++++++++++++ 2 files changed, 217 insertions(+) create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-endianness-01.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-endianness-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-endianness-01.reference_output new file mode 100644 index 000000000..34c79cda8 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-endianness-01.reference_output @@ -0,0 +1,25 @@ +aabbccdd # Test 5.3.2.4: M mode little endian load/store word of 0xAABBCCDD # NOTE: the memory was already filled with's so subword overwrite some, but not all of them. this is why the values are filled with deadbeefs, rather than 00's or ff's +deadccdd # M mode little endian load/store halfword of 0xAABBCCDD # NOTE: since we're doing a store that matches the width of the load, we cut out all the sign extension +deadbedd # M mode little endian load/store byte of 0xAABBCCDD +ddccbbaa # M mode big endian load/store word of 0xDDCCBBAA +deadbbaa # M mode big endian load/store halfword of 0xDDCCBBAA +deadbeaa # M mode big endian load/store byte of 0xDDCCBBAA +0000000b # ecall after going from M mode to S mode +aabbccdd # S mode little endian load/store word of 0xAABBCCDD +deadccdd # S mode little endian load/store halfword of 0xAABBCCDD +deadbedd # S mode little endian load/store byte of 0xAABBCCDD +00000009 # ecall after going from S mode to M mode +0000000b # ecall after going from M mode to S mode +ddccbbaa # S mode big endian load/store word of 0xDDCCBBAA +deadbbaa # S mode big endian load/store halfword of 0xDDCCBBAA +deadbeaa # S mode big endian load/store byte of 0xDDCCBBAA +00000009 # ecall after going from S mode to U mode +aabbccdd # U mode little endian load/store word of 0xAABBCCDD +deadccdd # U mode little endian load/store halfword of 0xAABBCCDD +deadbedd # U mode little endian load/store byte of 0xAABBCCDD +00000008 # ecall after going from U mode to M mode +0000000b # ecall after going from M mode to U mode +ddccbbaa # U mode big endian load/store word of 0xDDCCBBAA +deadbbaa # U mode big endian load/store halfword of 0xDDCCBBAA +deadbeaa # U mode big endian load/store byte of 0xDDCCBBAA +00000008 # ecall after ending tests in U mode diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S new file mode 100644 index 000000000..19433cda5 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-endianness-01.S @@ -0,0 +1,192 @@ +/////////////////////////////////////////// +// +// WALLY-endianness +// +// Author: Kip Macsai-Goren +// +// Created 2022-09-05 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-32.h" + +RVTEST_ISA("RV32I") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True; def NO_SAIL=True;",endianness) + +INIT_TESTS + +TRAP_HANDLER m + +// Test 5.3.2.4: testing that accesses to sub-word memory acceses not on a word boundary go +// correctly with the relevant status bit indicating endianness for each mode. +// do this by going to each mode with and testing loads with the big endian bit on and off work correctly + +// *** It appears Sail has the MBE, SBE, and UBE bits of mstatus hardwired to zero + +// M Mode little Endianness tests: + +li x28, 0xAABBCCDD +li x29, 0x8000F000 +sw x28, 0(x29) // value stored in memory as 0xAABBCCDD + +lw x30, 0(x29) // test load word, should read out 0xAABBCCDD +sw x30, 0(t1) // test store word, should save 0xAABBCCDD +addi t1, t1, 4 +addi a6, a6, 4 + +lh x30, 0(x29) // test load half, should read out 0xCCDD +sh x30, 0(t1) // test store half, should save 0xCCDD +addi t1, t1, 4 +addi a6, a6, 4 + +lb x30, 0(x29) // test load byte, should read out 0xDD +sb x30, 0(t1) // test store byte, should save 0xDD +addi t1, t1, 4 +addi a6, a6, 4 + +li x28, 0x2000000000 +csrs mstatus, x28 // turn on big endianness for M mode + +// M mode Big Endianness tests +// In big endian modes, all values are sign extended to the right, rather than left + +li x28, 0xAABBCCDD +li x29, 0x8000F000 +sw x28, 0(x29) // value stored in memory as 0xDDCCBBAA + +lw x30, 0(x29) // test load word, should read out 0xAABBCCDD +sw x30, 0(t1) // test store word, should save 0xDDCCBBAA +addi t1, t1, 4 +addi a6, a6, 4 + +lh x30, 0(x29) // test load half, should read out 0xAABB +sh x30, 0(t1) // test store half, should save 0xBBAA +addi t1, t1, 4 +addi a6, a6, 4 + +lb x30, 0(x29) // test load byte, should read out 0xAA +sb x30, 0(t1) // test store byte, should save 0xAA +addi t1, t1, 4 +addi a6, a6, 4 + +li x28, 0x2000000000 +csrc mstatus, x28 // Turn off big endianness for M mode before going into the trap handler + +GOTO_S_MODE + +// S mode Little endian tests + +li x28, 0xAABBCCDD +li x29, 0x8000F000 +sd x28, 0(x29) // value stored in memory as 0xAABBCCDD + +lw x30, 0(x29) // test load word, should read out 0xAABBCCDD +sw x30, 0(t1) // test store word, should save 0xAABBCCDD +addi t1, t1, 4 +addi a6, a6, 4 + +lh x30, 0(x29) // test load half, should read out 0xCCDD +sh x30, 0(t1) // test store half, should save 0xCCDD +addi t1, t1, 4 +addi a6, a6, 4 + +lb x30, 0(x29) // test load byte, should read out 0xDD +sb x30, 0(t1) // test store byte, should save 0xDD +addi t1, t1, 4 +addi a6, a6, 4 + +GOTO_M_MODE // Go back to M mode to be able to toggle SBE bit of mstatus + +li x28, 0x1000000000 +csrs mstatus, x28 // turn on big endianness for S mode + +GOTO_S_MODE + +// S mode Big endian tests + +li x28, 0xAABBCCDD +li x29, 0x8000F000 +sd x28, 0(x29) // value stored in memory as 0xDDCCBBAA + +lw x30, 0(x29) // test load word, should read out 0xAABBCCDD +sw x30, 0(t1) // test store word, should save 0xDDCCBBAA +addi t1, t1, 4 +addi a6, a6, 4 + +lh x30, 0(x29) // test load half, should read out 0xAABB +sh x30, 0(t1) // test store half, should save 0xBBAA +addi t1, t1, 4 +addi a6, a6, 4 + +lb x30, 0(x29) // test load byte, should read out 0xAA +sb x30, 0(t1) // test store byte, should save 0xAA +addi t1, t1, 4 +addi a6, a6, 4 + +GOTO_U_MODE + +// U mode Little endian tests + +li x28, 0xAABBCCDD +li x29, 0x8000F000 +sd x28, 0(x29) // value stored in memory as 0xAABBCCDD + +lw x30, 0(x29) // test load word, should read out 0xAABBCCDD +sw x30, 0(t1) // test store word, should save 0xAABBCCDD +addi t1, t1, 4 +addi a6, a6, 4 + +lh x30, 0(x29) // test load half, should read out 0xCCDD +sh x30, 0(t1) // test store half, should save 0xCCDD +addi t1, t1, 4 +addi a6, a6, 4 + +lb x30, 0(x29) // test load byte, should read out 0xDD +sb x30, 0(t1) // test store byte, should save 0xDD +addi t1, t1, 4 +addi a6, a6, 4 + +GOTO_M_MODE // go to M mode in order to be able to toggle the UBE bit + +li x28, 0x40 +csrs mstatus, x28 // turn on big endianness for U mode + +GOTO_U_MODE + +// U mode Big endian tests + +li x28, 0xAABBCCDD +li x29, 0x8000F000 +sd x28, 0(x29) // value stored in memory as 0xDDCCBBAA + +lw x30, 0(x29) // test load word, should read out 0xAABBCCDD +sw x30, 0(t1) // test store word, should save 0xDDCCBBAA +addi t1, t1, 4 +addi a6, a6, 4 + +lh x30, 0(x29) // test load half, should read out 0xAABB +sh x30, 0(t1) // test store half, should save 0xBBAA +addi t1, t1, 4 +addi a6, a6, 4 + +lb x30, 0(x29) // test load byte, should read out 0xAA +sb x30, 0(t1) // test store byte, should save 0xAA +addi t1, t1, 4 +addi a6, a6, 4 + +END_TESTS + +TEST_STACK_AND_DATA \ No newline at end of file From 3f4c825a1a7cf0d8990f19c9b538e654b029a53d Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Sun, 18 Sep 2022 00:11:29 +0000 Subject: [PATCH 4/6] added mstatus uxl, sxl bit tests (not tested in regression yet) --- .../WALLY-status-xlen-01.reference_output | 4 ++ .../privilege/src/WALLY-status-xlen-01.S | 51 +++++++++++++++++++ 2 files changed, 55 insertions(+) create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-xlen-01.reference_output create mode 100644 tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-xlen-01.S diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-xlen-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-xlen-01.reference_output new file mode 100644 index 000000000..f9469d56a --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-xlen-01.reference_output @@ -0,0 +1,4 @@ +00000000 # Test *** Number : Read out SXL, UXL of mstatus as 2 and 2 for 64 bit systems +0000000a +00000000 # read of read-only uxl, sxl bits after attmepted write +0000000a diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-xlen-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-xlen-01.S new file mode 100644 index 000000000..aaeaef110 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-xlen-01.S @@ -0,0 +1,51 @@ +/////////////////////////////////////////// +// +// WALLY-status-xlen +// +// Author: Kip Macsai-Goren +// +// Created 2022-09-17 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-64.h" + +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",endianness) + +INIT_TESTS + +TRAP_HANDLER m + +// Test ***Number: check that the UXL and SXL bits of mstatus are read only and the correct value (2 for 64 bit systems) + +csrr x28, mstatus +li x29, 0xF00000000 // mask bits for uxl and sxl +and x28, x28, x29 +sd x28, 0(t1) // should store 0xA00000000 to memory +addi t1, t1, 8 +addi a6, a6, 8 + +csrs mstatus, x29 // attempt to write to uxl and sxl, should not work +csrr x28, mstatus +and x28, x28, x29 +sd x28, 0(t1) // should store 0xA00000000 to memory +addi t1, t1, 8 +addi a6, a6, 8 + +END_TESTS + +TEST_STACK_AND_DATA From cc1ba84637a7abfd3283cd492b5a7c5d1eae5dcf Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 17 Sep 2022 20:30:01 -0500 Subject: [PATCH 5/6] Found the ahb burst bug. We had instruction fetches fixed HSIZE = 2 (4 bytes) for all requests. It should be HSIZE = 3 (8 bytes) for cache fetches and 4 for uncached reads. The reason this worked for non burst is the DDR4 memory controller returns the full double word even for 4 byte reads. In burst mode the second beat ending up pointing to the next 4 bytes rather than the next 8 bytes. --- pipelined/src/ebu/ahbinterface.sv | 3 ++- pipelined/src/ebu/ahbmulticontroller.sv | 26 ++++++++++------------- pipelined/src/ifu/ifu.sv | 4 +++- pipelined/src/lsu/lsu.sv | 3 ++- pipelined/src/wally/wallypipelinedcore.sv | 24 +++++++++++---------- 5 files changed, 31 insertions(+), 29 deletions(-) diff --git a/pipelined/src/ebu/ahbinterface.sv b/pipelined/src/ebu/ahbinterface.sv index c0b360eeb..689806a6e 100644 --- a/pipelined/src/ebu/ahbinterface.sv +++ b/pipelined/src/ebu/ahbinterface.sv @@ -34,7 +34,7 @@ `include "wally-config.vh" -module ahbinterface #(parameter WRITEABLE = 0) +module ahbinterface #(parameter WRITEABLE = 0) // **** modify to use LSU/ifu parameter to control widths of buses ( input logic HCLK, HRESETn, @@ -57,6 +57,7 @@ module ahbinterface #(parameter WRITEABLE = 0) logic CaptureEn; + /// *** only 32 bit for IFU. flopen #(`XLEN) fb(.clk(HCLK), .en(CaptureEn), .d(HRDATA), .q(ReadDataWord)); if(WRITEABLE) begin diff --git a/pipelined/src/ebu/ahbmulticontroller.sv b/pipelined/src/ebu/ahbmulticontroller.sv index b6141737d..7c86e1e7e 100644 --- a/pipelined/src/ebu/ahbmulticontroller.sv +++ b/pipelined/src/ebu/ahbmulticontroller.sv @@ -41,6 +41,7 @@ module ahbmulticontroller input logic clk, reset, // Signals from IFU input logic [`PA_BITS-1:0] IFUHADDR, + input logic [2:0] IFUHSIZE, input logic [2:0] IFUHBURST, input logic [1:0] IFUHTRANS, output logic IFUHREADY, @@ -69,28 +70,23 @@ module ahbmulticontroller (* mark_debug = "true" *) output logic HMASTLOCK ); - localparam ADRBITS = $clog2(`XLEN/8); // address bits for Byte Mask generator - typedef enum logic [1:0] {IDLE, ARBITRATE} statetype; statetype CurrState, NextState; - logic LSUGrant; - logic [ADRBITS-1:0] HADDRD; - logic [1:0] HSIZED; logic [1:0] save, restore, dis, sel; logic both; - logic [`PA_BITS-1:0] IFUHADDRSave, IFUHADDROut; - logic [1:0] IFUHTRANSSave, IFUHTRANSOut; - logic [2:0] IFUHBURSTSave, IFUHBURSTOut; + logic [`PA_BITS-1:0] IFUHADDROut; + logic [1:0] IFUHTRANSOut; + logic [2:0] IFUHBURSTOut; logic [2:0] IFUHSIZEOut; logic IFUHWRITEOut; - logic [`PA_BITS-1:0] LSUHADDRSave, LSUHADDROut; - logic [1:0] LSUHTRANSSave, LSUHTRANSOut; - logic [2:0] LSUHBURSTSave, LSUHBURSTOut; - logic [2:0] LSUHSIZESave, LSUHSIZEOut; - logic LSUHWRITESave, LSUHWRITEOut; + logic [`PA_BITS-1:0] LSUHADDROut; + logic [1:0] LSUHTRANSOut; + logic [2:0] LSUHBURSTOut; + logic [2:0] LSUHSIZEOut; + logic LSUHWRITEOut; logic IFUReq, LSUReq; logic IFUActive, LSUActive; @@ -112,7 +108,7 @@ module ahbmulticontroller // input stage IFU controllerinputstage IFUInput(.HCLK, .HRESETn, .Save(save[0]), .Restore(restore[0]), .Disable(dis[0]), .Request(IFUReq), .Active(IFUActive), - .HWRITEin(1'b0), .HSIZEin(3'b010), .HBURSTin(IFUHBURST), .HTRANSin(IFUHTRANS), .HADDRin(IFUHADDR), + .HWRITEin(1'b0), .HSIZEin(IFUHSIZE), .HBURSTin(IFUHBURST), .HTRANSin(IFUHTRANS), .HADDRin(IFUHADDR), .HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY), .HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYin(HREADY)); @@ -125,7 +121,7 @@ module ahbmulticontroller // output mux //*** rewrite for general number of controllers. assign HADDR = sel[1] ? LSUHADDROut : sel[0] ? IFUHADDROut : '0; - assign HSIZE = sel[1] ? LSUHSIZEOut : sel[0] ? 3'b010: '0; // Instruction reads are always 32 bits + assign HSIZE = sel[1] ? LSUHSIZEOut : sel[0] ? IFUHSIZEOut: '0; assign HBURST = sel[1] ? LSUHBURSTOut : sel[0] ? IFUHBURSTOut : '0; // If doing memory accesses, use LSUburst, else use Instruction burst. assign HTRANS = sel[1] ? LSUHTRANSOut : sel[0] ? IFUHTRANSOut: '0; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise assign HWRITE = sel[1] ? LSUHWRITEOut : sel[0] ? 1'b0 : '0; diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 548102429..cde1e02b5 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -41,6 +41,7 @@ module ifu ( (* mark_debug = "true" *) output logic IFUStallF, (* mark_debug = "true" *) output logic [2:0] IFUHBURST, (* mark_debug = "true" *) output logic [1:0] IFUHTRANS, +(* mark_debug = "true" *) output logic [2:0] IFUHSIZE, (* mark_debug = "true" *) output logic IFUHWRITE, (* mark_debug = "true" *) input logic IFUHREADY, (* mark_debug = "true" *) output logic [`XLEN-1:0] PCF, @@ -234,7 +235,7 @@ module ifu ( ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE) ahbcacheinterface(.HCLK(clk), .HRESETn(~reset), .HRDATA, - .CacheRW, .HSIZE(), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), + .CacheRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr), .WordCount(), .SelUncachedAdr, .SelBusWord(), .CacheBusAck(ICacheBusAck), @@ -249,6 +250,7 @@ module ifu ( logic CaptureEn; logic [1:0] RW; assign RW = NonIROMMemRWM & ~{ITLBMissF, ITLBMissF}; + assign IFUHSIZE = 3'b010; ahbinterface #(0) ahbinterface(.HCLK(clk), .HRESETn(~reset), .HREADY(IFUHREADY), .HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(), diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 05857cb69..599c6803a 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -216,7 +216,8 @@ module lsu ( assign MemStage = CPUBusy | MemRWM[0] | reset; // 1 = M stage; 0 = E stage assign DTIMAdr = MemStage ? IEUAdrExtM : IEUAdrExtE; // zero extend or contract to PA_BITS /* verilator lint_on WIDTH */ - assign DTIMAccessRW = |MemRWM; + assign DTIMAccessRW = |MemRWM; + // *** Ross remove this. adrdec dtimdec(IEUAdrExtM, `DTIM_BASE, `DTIM_RANGE, `DTIM_SUPPORTED, DTIMAccessRW, 2'b10, 4'b1111, SelDTIM); // maybe we pull this out of the mmu? //assign NonDTIMMemRWM = MemRWM & ~{2{SelDTIM}}; // disable access to bus-based memory map when DTIM is selected assign NonDTIMMemRWM = MemRWM; // *** fix diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index dd7567a79..43b929abe 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -132,18 +132,19 @@ module wallypipelinedcore ( logic CommittedM; // AHB ifu interface - logic [`PA_BITS-1:0] IFUHADDR; - logic [2:0] IFUHBURST; - logic [1:0] IFUHTRANS; - logic IFUHWRITE; - logic IFUHREADY; + logic [`PA_BITS-1:0] IFUHADDR; + logic [2:0] IFUHBURST; + logic [1:0] IFUHTRANS; + logic [2:0] IFUHSIZE; + logic IFUHWRITE; + logic IFUHREADY; // AHB LSU interface - logic [`PA_BITS-1:0] LSUHADDR; - logic [`XLEN-1:0] LSUHWDATA; - logic [`XLEN/8-1:0] LSUHWSTRB; - logic LSUHWRITE; - logic LSUHREADY; + logic [`PA_BITS-1:0] LSUHADDR; + logic [`XLEN-1:0] LSUHWDATA; + logic [`XLEN/8-1:0] LSUHWSTRB; + logic LSUHWRITE; + logic LSUHREADY; logic BPPredWrongE; logic BPPredDirWrongM; @@ -172,7 +173,7 @@ module wallypipelinedcore ( .FlushF, .FlushD, .FlushE, .FlushM, // Fetch .HRDATA, .PCF, .IFUHADDR, - .IFUStallF, .IFUHBURST, .IFUHTRANS, + .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE, .ICacheAccess, .ICacheMiss, @@ -295,6 +296,7 @@ module wallypipelinedcore ( .IFUHBURST, .IFUHTRANS, .IFUHREADY, + .IFUHSIZE, // LSU interface .LSUHADDR, .LSUHWDATA, From 6250a65ede6c54657c789c082089414ae86eac34 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 17 Sep 2022 22:20:06 -0500 Subject: [PATCH 6/6] added new constraints for fpga. --- fpga/constraints/debug2.xdc | 213 ++++++++++++++++++++++++++---------- fpga/src/fpgaTop.v | 86 +++++++-------- 2 files changed, 201 insertions(+), 98 deletions(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 3bae41c45..e8921999f 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -71,22 +71,28 @@ create_debug_port u_ila_0 probe set_property port_width 6 [get_debug_ports u_ila_0/probe13] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW[11]} ]] + + create_debug_port u_ila_0 probe -set_property port_width 5 [get_debug_ports u_ila_0/probe14] +set_property port_width 64 [get_debug_ports u_ila_0/probe14] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] -connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[0]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[1]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[2]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[3]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[4]} ]] +connect_debug_port u_ila_0/probe14 [get_nets [list {HRDATAEXT[0]} {HRDATAEXT[1]} {HRDATAEXT[2]} {HRDATAEXT[3]} {HRDATAEXT[4]} {HRDATAEXT[5]} {HRDATAEXT[6]} {HRDATAEXT[7]} {HRDATAEXT[8]} {HRDATAEXT[9]} {HRDATAEXT[10]} {HRDATAEXT[11]} {HRDATAEXT[12]} {HRDATAEXT[13]} {HRDATAEXT[14]} {HRDATAEXT[15]} {HRDATAEXT[16]} {HRDATAEXT[17]} {HRDATAEXT[18]} {HRDATAEXT[19]} {HRDATAEXT[20]} {HRDATAEXT[21]} {HRDATAEXT[22]} {HRDATAEXT[23]} {HRDATAEXT[24]} {HRDATAEXT[25]} {HRDATAEXT[26]} {HRDATAEXT[27]} {HRDATAEXT[28]} {HRDATAEXT[29]} {HRDATAEXT[30]} {HRDATAEXT[31]} {HRDATAEXT[32]} {HRDATAEXT[33]} {HRDATAEXT[34]} {HRDATAEXT[35]} {HRDATAEXT[36]} {HRDATAEXT[37]} {HRDATAEXT[38]} {HRDATAEXT[39]} {HRDATAEXT[40]} {HRDATAEXT[41]} {HRDATAEXT[42]} {HRDATAEXT[43]} {HRDATAEXT[44]} {HRDATAEXT[45]} {HRDATAEXT[46]} {HRDATAEXT[47]} {HRDATAEXT[48]} {HRDATAEXT[49]} {HRDATAEXT[50]} {HRDATAEXT[51]} {HRDATAEXT[52]} {HRDATAEXT[53]} {HRDATAEXT[54]} {HRDATAEXT[55]} {HRDATAEXT[56]} {HRDATAEXT[57]} {HRDATAEXT[58]} {HRDATAEXT[59]} {HRDATAEXT[60]} {HRDATAEXT[61]} {HRDATAEXT[62]} {HRDATAEXT[63]} ]] + create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe15] +set_property port_width 1 [get_debug_ports u_ila_0/probe15] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] -connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[0]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[1]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[2]} ]] +connect_debug_port u_ila_0/probe15 [get_nets [list {HREADYEXT} ]] + create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe16] +set_property port_width 1 [get_debug_ports u_ila_0/probe16] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] -connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/r_DAT_Q[0]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/r_DAT_Q[1]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/r_DAT_Q[2]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/r_DAT_Q[3]} ]] +connect_debug_port u_ila_0/probe16 [get_nets [list {HRESPEXT} ]] + create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe17] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[0]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[1]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[2]} {wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState[3]} ]] + create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe18] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] @@ -118,18 +124,22 @@ set_property port_width 63 [get_debug_ports u_ila_0/probe23] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[63]} ]] + create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe24] +set_property port_width 1 [get_debug_ports u_ila_0/probe24] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] -connect_debug_port u_ila_0/probe24 [get_nets [list {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[0]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[1]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[2]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[3]} ]] +connect_debug_port u_ila_0/probe24 [get_nets [list {HSELEXT} ]] + create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe25] +set_property port_width 32 [get_debug_ports u_ila_0/probe25] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] -connect_debug_port u_ila_0/probe25 [get_nets [list {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/i_SD_DAT[0]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/i_SD_DAT[1]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/i_SD_DAT[2]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/i_SD_DAT[3]} ]] +connect_debug_port u_ila_0/probe25 [get_nets [list {HADDR[0]} {HADDR[1]} {HADDR[2]} {HADDR[3]} {HADDR[4]} {HADDR[5]} {HADDR[6]} {HADDR[7]} {HADDR[8]} {HADDR[9]} {HADDR[10]} {HADDR[11]} {HADDR[12]} {HADDR[13]} {HADDR[14]} {HADDR[15]} {HADDR[16]} {HADDR[17]} {HADDR[18]} {HADDR[19]} {HADDR[20]} {HADDR[21]} {HADDR[22]} {HADDR[23]} {HADDR[24]} {HADDR[25]} {HADDR[26]} {HADDR[27]} {HADDR[28]} {HADDR[29]} {HADDR[30]} {HADDR[31]} ]] + create_debug_port u_ila_0 probe -set_property port_width 12 [get_debug_ports u_ila_0/probe26] +set_property port_width 64 [get_debug_ports u_ila_0/probe26] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] -connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[0]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[1]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[2]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[3]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[4]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[5]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[6]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[7]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[8]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[9]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[10]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[11]} ]] +connect_debug_port u_ila_0/probe26 [get_nets [list {HWDATA[0]} {HWDATA[1]} {HWDATA[2]} {HWDATA[3]} {HWDATA[4]} {HWDATA[5]} {HWDATA[6]} {HWDATA[7]} {HWDATA[8]} {HWDATA[9]} {HWDATA[10]} {HWDATA[11]} {HWDATA[12]} {HWDATA[13]} {HWDATA[14]} {HWDATA[15]} {HWDATA[16]} {HWDATA[17]} {HWDATA[18]} {HWDATA[19]} {HWDATA[20]} {HWDATA[21]} {HWDATA[22]} {HWDATA[23]} {HWDATA[24]} {HWDATA[25]} {HWDATA[26]} {HWDATA[27]} {HWDATA[28]} {HWDATA[29]} {HWDATA[30]} {HWDATA[31]} {HWDATA[32]} {HWDATA[33]} {HWDATA[34]} {HWDATA[35]} {HWDATA[36]} {HWDATA[37]} {HWDATA[38]} {HWDATA[39]} {HWDATA[40]} {HWDATA[41]} {HWDATA[42]} {HWDATA[43]} {HWDATA[44]} {HWDATA[45]} {HWDATA[46]} {HWDATA[47]} {HWDATA[48]} {HWDATA[49]} {HWDATA[50]} {HWDATA[51]} {HWDATA[52]} {HWDATA[53]} {HWDATA[54]} {HWDATA[55]} {HWDATA[56]} {HWDATA[57]} {HWDATA[58]} {HWDATA[59]} {HWDATA[60]} {HWDATA[61]} {HWDATA[62]} {HWDATA[63]} ]] + create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe27] @@ -140,14 +150,18 @@ create_debug_port u_ila_0 probe set_property port_width 6 [get_debug_ports u_ila_0/probe28] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28] connect_debug_port u_ila_0/probe28 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/MIE_REGW[11]} ]] + + create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe29] +set_property port_width 1 [get_debug_ports u_ila_0/probe29] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29] -connect_debug_port u_ila_0/probe29 [get_nets [list {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/r_IC_OUT[0]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/r_IC_OUT[1]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/r_IC_OUT[2]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/r_IC_OUT[3]} ]] +connect_debug_port u_ila_0/probe29 [get_nets [list {HWRITE} ]] + create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe30] +set_property port_width 3 [get_debug_ports u_ila_0/probe30] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30] -connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[0]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[1]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[2]} {wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[3]} ]] +connect_debug_port u_ila_0/probe30 [get_nets [list {HSIZE[0]} {HSIZE[1]} {HSIZE[2]} ]] + create_debug_port u_ila_0 probe set_property port_width 2 [get_debug_ports u_ila_0/probe31] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31] @@ -178,22 +192,27 @@ create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe37] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37] connect_debug_port u_ila_0/probe37 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/EcallFaultM ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe38] +set_property port_width 3 [get_debug_ports u_ila_0/probe38] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38] -connect_debug_port u_ila_0/probe38 [get_nets [list wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_dat_fsm/i_DAT0_Q ]] +connect_debug_port u_ila_0/probe38 [get_nets [list {HBURST[0]} {HBURST[1]} {HBURST[2]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe39] +set_property port_width 2 [get_debug_ports u_ila_0/probe39] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39] -connect_debug_port u_ila_0/probe39 [get_nets [list wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_dat_fsm/i_DATA_CRC16_GOOD ]] +connect_debug_port u_ila_0/probe39 [get_nets [list {HTRANS[0]} {HTRANS[1]} ]] + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe40] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40] -connect_debug_port u_ila_0/probe40 [get_nets [list wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_CRC16 ]] +connect_debug_port u_ila_0/probe40 [get_nets [list {HREADY} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe41] +set_property port_width 4 [get_debug_ports u_ila_0/probe41] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41] -connect_debug_port u_ila_0/probe41 [get_nets [list wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_DAT_TIMES_OUT ]] +connect_debug_port u_ila_0/probe41 [get_nets [list {m_axi_awid[0]} {m_axi_awid[1]} {m_axi_awid[2]} {m_axi_awid[3]} ]] + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe42] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42] @@ -232,26 +251,33 @@ create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe50] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50] connect_debug_port u_ila_0/probe50 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/mretM ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe51] +set_property port_width 8 [get_debug_ports u_ila_0/probe51] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51] -connect_debug_port u_ila_0/probe51 [get_nets [list wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_clk_fsm/o_G_CLK_SD_EN ]] +connect_debug_port u_ila_0/probe51 [get_nets [list {m_axi_awlen[0]} {m_axi_awlen[1]} {m_axi_awlen[2]} {m_axi_awlen[3]} {m_axi_awlen[4]} {m_axi_awlen[5]} {m_axi_awlen[6]} {m_axi_awlen[7]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe52] +set_property port_width 2 [get_debug_ports u_ila_0/probe52] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52] -connect_debug_port u_ila_0/probe52 [get_nets [list wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/o_SD_CLK ]] +connect_debug_port u_ila_0/probe52 [get_nets [list {m_axi_awburst[0]} {m_axi_awburst[1]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe53] +set_property port_width 4 [get_debug_ports u_ila_0/probe53] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53] -connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/o_SD_CMD ]] +connect_debug_port u_ila_0/probe53 [get_nets [list {m_axi_awcache[0]} {m_axi_awcache[1]} {m_axi_awcache[2]} {m_axi_awcache[3]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe54] +set_property port_width 32 [get_debug_ports u_ila_0/probe54] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54] -connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/o_SD_CMD_OE ]] +connect_debug_port u_ila_0/probe54 [get_nets [list {m_axi_awaddr[0]} {m_axi_awaddr[1]} {m_axi_awaddr[2]} {m_axi_awaddr[3]} {m_axi_awaddr[4]} {m_axi_awaddr[5]} {m_axi_awaddr[6]} {m_axi_awaddr[7]} {m_axi_awaddr[8]} {m_axi_awaddr[9]} {m_axi_awaddr[10]} {m_axi_awaddr[11]} {m_axi_awaddr[12]} {m_axi_awaddr[13]} {m_axi_awaddr[14]} {m_axi_awaddr[15]} {m_axi_awaddr[16]} {m_axi_awaddr[17]} {m_axi_awaddr[18]} {m_axi_awaddr[19]} {m_axi_awaddr[20]} {m_axi_awaddr[21]} {m_axi_awaddr[22]} {m_axi_awaddr[23]} {m_axi_awaddr[24]} {m_axi_awaddr[25]} {m_axi_awaddr[26]} {m_axi_awaddr[27]} {m_axi_awaddr[28]} {m_axi_awaddr[29]} {m_axi_awaddr[30]} {m_axi_awaddr[31]} ]] + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe55] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55] -connect_debug_port u_ila_0/probe55 [get_nets [list wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_SD_CMD_OE ]] +connect_debug_port u_ila_0/probe55 [get_nets [list {m_axi_awvalid} ]] + + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe56] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56] @@ -260,10 +286,12 @@ create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe57] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57] connect_debug_port u_ila_0/probe57 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/OUT2b ]] + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe58] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58] -connect_debug_port u_ila_0/probe58 [get_nets [list wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q ]] +connect_debug_port u_ila_0/probe58 [get_nets [list {m_axi_awready} ]] + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe59] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59] @@ -304,20 +332,21 @@ create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe68] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe68] connect_debug_port u_ila_0/probe68 [get_nets [list wallypipelinedsoc/uncore.uncore/uart.uart/TXRDYb ]] + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe69] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69] -connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/w_IC_EN ]] +connect_debug_port u_ila_0/probe69 [get_nets [list {m_axi_awlock} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe70] +set_property port_width 64 [get_debug_ports u_ila_0/probe70] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70] -connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/w_IC_RST ]] +connect_debug_port u_ila_0/probe70 [get_nets [list {m_axi_wdata[0]} {m_axi_wdata[1]} {m_axi_wdata[2]} {m_axi_wdata[3]} {m_axi_wdata[4]} {m_axi_wdata[5]} {m_axi_wdata[6]} {m_axi_wdata[7]} {m_axi_wdata[8]} {m_axi_wdata[9]} {m_axi_wdata[10]} {m_axi_wdata[11]} {m_axi_wdata[12]} {m_axi_wdata[13]} {m_axi_wdata[14]} {m_axi_wdata[15]} {m_axi_wdata[16]} {m_axi_wdata[17]} {m_axi_wdata[18]} {m_axi_wdata[19]} {m_axi_wdata[20]} {m_axi_wdata[21]} {m_axi_wdata[22]} {m_axi_wdata[23]} {m_axi_wdata[24]} {m_axi_wdata[25]} {m_axi_wdata[26]} {m_axi_wdata[27]} {m_axi_wdata[28]} {m_axi_wdata[29]} {m_axi_wdata[30]} {m_axi_wdata[31]} {m_axi_wdata[32]} {m_axi_wdata[33]} {m_axi_wdata[34]} {m_axi_wdata[35]} {m_axi_wdata[36]} {m_axi_wdata[37]} {m_axi_wdata[38]} {m_axi_wdata[39]} {m_axi_wdata[40]} {m_axi_wdata[41]} {m_axi_wdata[42]} {m_axi_wdata[43]} {m_axi_wdata[44]} {m_axi_wdata[45]} {m_axi_wdata[46]} {m_axi_wdata[47]} {m_axi_wdata[48]} {m_axi_wdata[49]} {m_axi_wdata[50]} {m_axi_wdata[51]} {m_axi_wdata[52]} {m_axi_wdata[53]} {m_axi_wdata[54]} {m_axi_wdata[55]} {m_axi_wdata[56]} {m_axi_wdata[57]} {m_axi_wdata[58]} {m_axi_wdata[59]} {m_axi_wdata[60]} {m_axi_wdata[61]} {m_axi_wdata[62]} {m_axi_wdata[63]} ]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe71] +set_property port_width 8 [get_debug_ports u_ila_0/probe71] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe71] -connect_debug_port u_ila_0/probe71 [get_nets [list wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/w_IC_UP_DOWN ]] +connect_debug_port u_ila_0/probe71 [get_nets [list {m_axi_wstrb[0]} {m_axi_wstrb[1]} {m_axi_wstrb[2]} {m_axi_wstrb[3]} {m_axi_wstrb[4]} {m_axi_wstrb[5]} {m_axi_wstrb[6]} {m_axi_wstrb[7]} ]] create_debug_port u_ila_0 probe @@ -753,37 +782,36 @@ set_property port_width 8 [get_debug_ports u_ila_0/probe155] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe155] connect_debug_port u_ila_0/probe155 [get_nets [list {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[0]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[1]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[2]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[3]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[4]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[5]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[6]} {wallypipelinedsoc/uncore.uncore/uart.uart/u/LCR[7]} ]] - create_debug_port u_ila_0 probe -set_property port_width 12 [get_debug_ports u_ila_0/probe156] +set_property port_width 1 [get_debug_ports u_ila_0/probe156] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe156] -connect_debug_port u_ila_0/probe156 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/requests[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[10]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[11]} {wallypipelinedsoc/uncore.uncore/plic.plic/requests[12]}]] - +connect_debug_port u_ila_0/probe156 [get_nets [list {m_axi_wlast} ]] + create_debug_port u_ila_0 probe -set_property port_width 12 [get_debug_ports u_ila_0/probe157] +set_property port_width 1 [get_debug_ports u_ila_0/probe157] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe157] -connect_debug_port u_ila_0/probe157 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[10]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[11]} {wallypipelinedsoc/uncore.uncore/plic.plic/intInProgress[12]}]] - +connect_debug_port u_ila_0/probe157 [get_nets [list {m_axi_wvalid} ]] + create_debug_port u_ila_0 probe -set_property port_width 12 [get_debug_ports u_ila_0/probe158] +set_property port_width 1 [get_debug_ports u_ila_0/probe158] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe158] -connect_debug_port u_ila_0/probe158 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[10]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[11]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPending[12]}]] - +connect_debug_port u_ila_0/probe158 [get_nets [list {m_axi_wready} ]] create_debug_port u_ila_0 probe -set_property port_width 70 [get_debug_ports u_ila_0/probe159] +set_property port_width 4 [get_debug_ports u_ila_0/probe159] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe159] -connect_debug_port u_ila_0/probe159 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][1][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][2][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][3][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][4][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][5][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][6][10]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][2]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][3]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][4]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][5]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][6]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][7]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][8]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][9]} {wallypipelinedsoc/uncore.uncore/plic.plic/irqMatrix[1][7][10]} ]] +connect_debug_port u_ila_0/probe159 [get_nets [list {m_axi_bid[0]} {m_axi_bid[1]} {m_axi_bid[2]} {m_axi_bid[3]} ]] create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe160] +set_property port_width 2 [get_debug_ports u_ila_0/probe160] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe160] -connect_debug_port u_ila_0/probe160 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][0]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intPriority[10][2]} ]] - +connect_debug_port u_ila_0/probe160 [get_nets [list {m_axi_bresp[0]} {m_axi_bresp[1]} ]] + create_debug_port u_ila_0 probe -set_property port_width 10 [get_debug_ports u_ila_0/probe161] +set_property port_width 1 [get_debug_ports u_ila_0/probe161] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe161] -connect_debug_port u_ila_0/probe161 [get_nets [list {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[1]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[2]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[3]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[4]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[5]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[6]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[7]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[8]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[9]} {wallypipelinedsoc/uncore.uncore/plic.plic/intEn[1]__0[10]} ]] +connect_debug_port u_ila_0/probe161 [get_nets [list {m_axi_bvalid} ]] + create_debug_port u_ila_0 probe set_property port_width 3 [get_debug_ports u_ila_0/probe162] @@ -826,3 +854,78 @@ set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe169] connect_debug_port u_ila_0/probe169 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[0]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[1]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[2]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[3]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[4]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[5]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[6]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[7]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[8]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[9]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[10]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[11]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[12]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[13]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[14]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[15]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[16]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[17]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[18]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[19]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[20]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[21]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[22]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[23]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[24]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[25]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[26]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[27]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[28]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[29]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[30]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[31]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[32]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[33]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[34]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[35]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[36]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[37]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[38]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[39]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[40]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[41]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[42]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[43]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[44]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[45]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[46]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[47]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[48]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[49]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[50]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[51]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[52]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[53]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[54]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[55]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[56]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[57]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[58]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[59]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[60]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[61]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[62]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[63]}]] +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe170] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe170] +connect_debug_port u_ila_0/probe170 [get_nets [list {m_axi_bready} ]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe171] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe171] +connect_debug_port u_ila_0/probe171 [get_nets [list {m_axi_arid[0]} {m_axi_arid[1]} {m_axi_arid[2]} {m_axi_arid[3]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe172] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe172] +connect_debug_port u_ila_0/probe172 [get_nets [list {m_axi_arlen[0]} {m_axi_arlen[1]} {m_axi_arlen[2]} {m_axi_arlen[3]} {m_axi_arlen[4]} {m_axi_arlen[5]} {m_axi_arlen[6]} {m_axi_arlen[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 3 [get_debug_ports u_ila_0/probe173] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe173] +connect_debug_port u_ila_0/probe173 [get_nets [list {m_axi_arsize[0]} {m_axi_arsize[1]} {m_axi_arsize[2]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe174] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe174] +connect_debug_port u_ila_0/probe174 [get_nets [list {m_axi_arburst[0]} {m_axi_arburst[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe175] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe175] +connect_debug_port u_ila_0/probe175 [get_nets [list {m_axi_arcache[0]} {m_axi_arcache[1]} {m_axi_arcache[2]} {m_axi_arcache[3]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe176] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe176] +connect_debug_port u_ila_0/probe176 [get_nets [list {m_axi_arvalid} ]] + +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe177] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe177] +connect_debug_port u_ila_0/probe177 [get_nets [list {m_axi_araddr[0]} {m_axi_araddr[1]} {m_axi_araddr[2]} {m_axi_araddr[3]} {m_axi_araddr[4]} {m_axi_araddr[5]} {m_axi_araddr[6]} {m_axi_araddr[7]} {m_axi_araddr[8]} {m_axi_araddr[9]} {m_axi_araddr[10]} {m_axi_araddr[11]} {m_axi_araddr[12]} {m_axi_araddr[13]} {m_axi_araddr[14]} {m_axi_araddr[15]} {m_axi_araddr[16]} {m_axi_araddr[17]} {m_axi_araddr[18]} {m_axi_araddr[19]} {m_axi_araddr[20]} {m_axi_araddr[21]} {m_axi_araddr[22]} {m_axi_araddr[23]} {m_axi_araddr[24]} {m_axi_araddr[25]} {m_axi_araddr[26]} {m_axi_araddr[27]} {m_axi_araddr[28]} {m_axi_araddr[29]} {m_axi_araddr[30]} {m_axi_araddr[31]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe178] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe178] +connect_debug_port u_ila_0/probe178 [get_nets [list {m_axi_arready} ]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe179] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe179] +connect_debug_port u_ila_0/probe179 [get_nets [list {m_axi_rid[0]} {m_axi_rid[1]} {m_axi_rid[2]} {m_axi_rid[3]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe180] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe180] +connect_debug_port u_ila_0/probe180 [get_nets [list {m_axi_rdata[0]} {m_axi_rdata[1]} {m_axi_rdata[2]} {m_axi_rdata[3]} {m_axi_rdata[4]} {m_axi_rdata[5]} {m_axi_rdata[6]} {m_axi_rdata[7]} {m_axi_rdata[8]} {m_axi_rdata[9]} {m_axi_rdata[10]} {m_axi_rdata[11]} {m_axi_rdata[12]} {m_axi_rdata[13]} {m_axi_rdata[14]} {m_axi_rdata[15]} {m_axi_rdata[16]} {m_axi_rdata[17]} {m_axi_rdata[18]} {m_axi_rdata[19]} {m_axi_rdata[20]} {m_axi_rdata[21]} {m_axi_rdata[22]} {m_axi_rdata[23]} {m_axi_rdata[24]} {m_axi_rdata[25]} {m_axi_rdata[26]} {m_axi_rdata[27]} {m_axi_rdata[28]} {m_axi_rdata[29]} {m_axi_rdata[30]} {m_axi_rdata[31]} {m_axi_rdata[32]} {m_axi_rdata[33]} {m_axi_rdata[34]} {m_axi_rdata[35]} {m_axi_rdata[36]} {m_axi_rdata[37]} {m_axi_rdata[38]} {m_axi_rdata[39]} {m_axi_rdata[40]} {m_axi_rdata[41]} {m_axi_rdata[42]} {m_axi_rdata[43]} {m_axi_rdata[44]} {m_axi_rdata[45]} {m_axi_rdata[46]} {m_axi_rdata[47]} {m_axi_rdata[48]} {m_axi_rdata[49]} {m_axi_rdata[50]} {m_axi_rdata[51]} {m_axi_rdata[52]} {m_axi_rdata[53]} {m_axi_rdata[54]} {m_axi_rdata[55]} {m_axi_rdata[56]} {m_axi_rdata[57]} {m_axi_rdata[58]} {m_axi_rdata[59]} {m_axi_rdata[60]} {m_axi_rdata[61]} {m_axi_rdata[62]} {m_axi_rdata[63]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe181] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe181] +connect_debug_port u_ila_0/probe181 [get_nets [list {m_axi_rresp[0]} {m_axi_rresp[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe182] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe182] +connect_debug_port u_ila_0/probe182 [get_nets [list {m_axi_rvalid} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe183] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe183] +connect_debug_port u_ila_0/probe183 [get_nets [list {m_axi_rlast} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe184] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe184] +connect_debug_port u_ila_0/probe184 [get_nets [list {m_axi_rready} ]] + diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index d299e5512..c0445b204 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -70,21 +70,21 @@ module fpgaTop wire peripheral_aresetn; wire mb_reset; - wire [`AHBW-1:0] HRDATAEXT; - wire HREADYEXT; - wire HRESPEXT; - wire HSELEXT; wire HCLKOpen; wire HRESETnOpen; - wire [31:0] HADDR; - wire [`AHBW-1:0] HWDATA; - wire HWRITE; - wire [2:0] HSIZE; - wire [2:0] HBURST; +(* mark_debug = "true" *) wire [`AHBW-1:0] HRDATAEXT; +(* mark_debug = "true" *) wire HREADYEXT; +(* mark_debug = "true" *) wire HRESPEXT; +(* mark_debug = "true" *) wire HSELEXT; +(* mark_debug = "true" *) wire [31:0] HADDR; +(* mark_debug = "true" *) wire [`AHBW-1:0] HWDATA; +(* mark_debug = "true" *) wire HWRITE; +(* mark_debug = "true" *) wire [2:0] HSIZE; +(* mark_debug = "true" *) wire [2:0] HBURST; +(* mark_debug = "true" *) wire [1:0] HTRANS; +(* mark_debug = "true" *) wire HREADY; wire [3:0] HPROT; - wire [1:0] HTRANS; wire HMASTLOCK; - wire HREADY; @@ -94,41 +94,41 @@ module fpgaTop wire SDCCmdOE; wire SDCCmdOut; - wire [3:0] m_axi_awid; - wire [7:0] m_axi_awlen; - wire [2:0] m_axi_awsize; - wire [1:0] m_axi_awburst; - wire [3:0] m_axi_awcache; - wire [31:0] m_axi_awaddr; +(* mark_debug = "true" *) wire [3:0] m_axi_awid; +(* mark_debug = "true" *) wire [7:0] m_axi_awlen; +(* mark_debug = "true" *) wire [2:0] m_axi_awsize; +(* mark_debug = "true" *) wire [1:0] m_axi_awburst; +(* mark_debug = "true" *) wire [3:0] m_axi_awcache; +(* mark_debug = "true" *) wire [31:0] m_axi_awaddr; wire [2:0] m_axi_awprot; - wire m_axi_awvalid; - wire m_axi_awready; - wire m_axi_awlock; - wire [63:0] m_axi_wdata; - wire [7:0] m_axi_wstrb; - wire m_axi_wlast; - wire m_axi_wvalid; - wire m_axi_wready; - wire [3:0] m_axi_bid; - wire [1:0] m_axi_bresp; - wire m_axi_bvalid; - wire m_axi_bready; - wire [3:0] m_axi_arid; - wire [7:0] m_axi_arlen; - wire [2:0] m_axi_arsize; - wire [1:0] m_axi_arburst; +(* mark_debug = "true" *) wire m_axi_awvalid; +(* mark_debug = "true" *) wire m_axi_awready; +(* mark_debug = "true" *) wire m_axi_awlock; +(* mark_debug = "true" *) wire [63:0] m_axi_wdata; +(* mark_debug = "true" *) wire [7:0] m_axi_wstrb; +(* mark_debug = "true" *) wire m_axi_wlast; +(* mark_debug = "true" *) wire m_axi_wvalid; +(* mark_debug = "true" *) wire m_axi_wready; +(* mark_debug = "true" *) wire [3:0] m_axi_bid; +(* mark_debug = "true" *) wire [1:0] m_axi_bresp; +(* mark_debug = "true" *) wire m_axi_bvalid; +(* mark_debug = "true" *) wire m_axi_bready; +(* mark_debug = "true" *) wire [3:0] m_axi_arid; +(* mark_debug = "true" *) wire [7:0] m_axi_arlen; +(* mark_debug = "true" *) wire [2:0] m_axi_arsize; +(* mark_debug = "true" *) wire [1:0] m_axi_arburst; wire [2:0] m_axi_arprot; - wire [3:0] m_axi_arcache; - wire m_axi_arvalid; - wire [31:0] m_axi_araddr; +(* mark_debug = "true" *) wire [3:0] m_axi_arcache; +(* mark_debug = "true" *) wire m_axi_arvalid; +(* mark_debug = "true" *) wire [31:0] m_axi_araddr; wire m_axi_arlock; - wire m_axi_arready; - wire [3:0] m_axi_rid; - wire [63:0] m_axi_rdata; - wire [1:0] m_axi_rresp; - wire m_axi_rvalid; - wire m_axi_rlast; - wire m_axi_rready; +(* mark_debug = "true" *) wire m_axi_arready; +(* mark_debug = "true" *) wire [3:0] m_axi_rid; +(* mark_debug = "true" *) wire [63:0] m_axi_rdata; +(* mark_debug = "true" *) wire [1:0] m_axi_rresp; +(* mark_debug = "true" *) wire m_axi_rvalid; +(* mark_debug = "true" *) wire m_axi_rlast; +(* mark_debug = "true" *) wire m_axi_rready; wire [3:0] BUS_axi_arregion; wire [3:0] BUS_axi_arqos;