From 24942f905463d76a05765828b637cb6b2f2b41a5 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 12 Nov 2023 20:23:14 -0800 Subject: [PATCH] DivStickyM no longer mysteriously needs to be gated with SqrtM after divder improvemenst --- src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index cb1f56db7..0b358909a 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -86,9 +86,10 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) ( ////////////////////////// // If the result is not exact, the sticky should be set - assign DivStickyM = ~WZeroM & ~(SpecialCaseM & SqrtM); // ***unsure why SpecialCaseM has to be gated by SqrtM, but otherwise fails regression on divide +// assign DivStickyM = ~WZeroM & ~(SpecialCaseM & SqrtM); // ***unsure why SpecialCaseM has to be gated by SqrtM, but otherwise fails regression on divide + assign DivStickyM = ~WZeroM & ~(SpecialCaseM); - // Determine if sticky bit is negative // *** look for ways to optimize this. Shift shouldn't be needed. + // Determine if sticky bit is negative assign Sum = WC + WS; assign NegStickyM = Sum[P.DIVb+3]; mux2 #(P.DIVb+1) preummux(FirstU, FirstUM, NegStickyM, PreUmM); // Select U or U-1 depending on negative sticky bit