diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 806709f08..9d4f78547 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -61,7 +61,6 @@ string tvpaths[] = '{ "bd_speedopt_speed/src/nsichneu/nsichneu", "bd_speedopt_speed/src/picojpeg/picojpeg", // "bd_speedopt_speed/src/primecount/primecount", - "bd_speedopt_speed/src/qrduino/qrduino", "bd_speedopt_speed/src/sglib-combined/sglib-combined", "bd_speedopt_speed/src/slre/slre", "bd_speedopt_speed/src/st/st", @@ -82,7 +81,7 @@ string tvpaths[] = '{ "bd_sizeopt_speed/src/nettle-sha256/nettle-sha256", "bd_sizeopt_speed/src/nsichneu/nsichneu", "bd_sizeopt_speed/src/picojpeg/picojpeg", - "bd_sizeopt_speed/src/primecount/primecount", + // "bd_sizeopt_speed/src/primecount/primecount", "bd_sizeopt_speed/src/qrduino/qrduino", "bd_sizeopt_speed/src/sglib-combined/sglib-combined", "bd_sizeopt_speed/src/slre/slre", diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-plic-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-plic-01.reference_output index 8c6b8ef6a..6d3b051b1 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-plic-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-plic-01.reference_output @@ -214,23 +214,23 @@ 00000003 # claim gives 3 for ID of GPIO 00000400 # check GPIO interrupt pending cleared after claim 00000000 # check no interrupts pending -00000000 # read sip +00000000 # read sip (7.4) 00000408 # check GPIO and UART interrupt pending on intPending0 00000000 # nothing in claim register 00000408 # check GPIO and UART interrupt pending on intPending0 00000000 # check no interrupts pending -00000200 # read sip +00000200 # read sip (7.5) 00000408 # check GPIO and UART interrupt pending on intPending0 00000003 # claim gives 3 for ID of GPIO 00000400 # check GPIO interrupt pending cleared after claim 00000000 # check no interrupts pending -00000000 # read sip +00000000 # read sip (7.6) 00000408 # check GPIO and UART interrupt pending on intPending0 00000000 # nothing in claim register 00000408 # check GPIO and UART interrupt pending on intPending0 00000000 # check no interrupts pending 00000009 # output from ecall in supervisor mode -00000800 # MEIP set +00000800 # MEIP set (8.0) 00000408 # check GPIO and UART interrupt pending on intPending0 0000000A # claim UART 00000008 # GPIO interrupt pending after UART claimcomp diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-uart-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-uart-01.reference_output index 457bc35c8..899884395 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-uart-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-uart-01.reference_output @@ -15,7 +15,7 @@ 00000101 # Transmit 7 bits 0000007F 00000101 # Transmit 8 bits -00000080 +ffffff80 00000002 # Transmission interrupt tests 00000401 # Interrupt generated by finished transmission 00000004 @@ -27,7 +27,18 @@ 00000000 00000011 00000001 - +00000000 # DSR Test +00000032 +00000001 +00000000 # RI Test +00000034 +00000001 +00000000 # DCD Test +ffffffB8 +00000001 +ffffffC2 # FIFO interrupt +0000C101 +00000000 0000000b # ecall from test termination diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index 4e2b075e6..e69b54f9d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -965,7 +965,6 @@ read08_test: // address to read in t3, expected 8 bit value in t4 (unused, but there for your perusal). li t2, 0xBAD // bad value that will be overwritten on good reads. lb t2, 0(t3) - andi t2, t2, 0xFF // mask to lower 8 bits sw t2, 0(t1) addi t1, t1, 4 addi a6, a6, 4 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S index 1547cee43..8aa141136 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S @@ -135,9 +135,33 @@ test_cases: .4byte UART_MSR, 0x00, write08_test # clear MSR .4byte UART_IER, 0x08, write08_test # enable MODEM Status interrupts .4byte UART_IIR, 0x01, read08_test # no interrupts pending -.4byte UART_MCR, 0x02, write08_test # Cause DCTS interrupt +.4byte UART_MCR, 0x12, write08_test # Cause DCTS interrupt .4byte UART_IIR, 0x00, read08_test # MODEM interrupt .4byte UART_MSR, 0x11, read08_test # Read MSR to clear interrupt .4byte UART_IIR, 0x01, read08_test # interrupt cleared by reading MSR +.4byte UART_MCR, 0x13, write08_test # Set DSR high +.4byte UART_IIR, 0x00, read08_test # MODEM interrupt +.4byte UART_MSR, 0x32, read08_test # Read MSR to clear interrupt +.4byte UART_IIR, 0x01, read08_test # Interrupt cleared by reading MSR +.4byte UART_MCR, 0x17, write08_test # Set RIb low and keep CTS and DSR +.4byte UART_MCR, 0x13, write08_test # Set RIb high and keep CTS and DSR +.4byte UART_IIR, 0x00, read08_test # MODEM interrupt +.4byte UART_MSR, 0x34, read08_test # Read MSR to clear interrupt +.4byte UART_IIR, 0x01, read08_test # Interrupt cleared by reading MSR +.4byte UART_MCR, 0x1B, write08_test # Set DCD high and keep CTS and DSR +.4byte UART_IIR, 0x00, read08_test # MODEM interrupt +.4byte UART_MSR, 0xb8, read08_test # Read MSR to clear interrupt +.4byte UART_IIR, 0x01, read08_test # Interrupt cleared by reading MSR +.4byte UART_MCR, 0x10, write08_test # Clear MCR +.4byte UART_MSR, 0x00, write08_test # Clear MSR + +# =========== FIFO interrupts =========== + +.4byte UART_IER, 0x07, write08_test # enable data available, buffer empty, and line status interrupts +.4byte UART_FCR, 0x41, write08_test # Set FIFO threshold to 4 and enable FIFO mode +.4byte UART_IIR, 0xC2, read08_test # Enabling FIFO sets top two bits of IIR +.4byte UART_THR, 0x00, write08_test # write 0 to transmit register +.4byte 0x0, 0xC101, uart_data_wait # no interrupts pending (transmitter interrupt squashed by early read) +.4byte UART_RBR, 0x00, read08_test # read 0 from buffer register .4byte 0x0, 0x0, terminate_test \ No newline at end of file