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Found bug in gshare.

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This commit is contained in:
Ross Thompson 2023-01-29 15:03:25 -06:00
parent 5fb3a669b1
commit 244885d3fa
4 changed files with 9 additions and 11 deletions
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3
pipelined/config/rv32gc/wally-config.vh
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@ -132,7 +132,8 @@
`define PLIC_UART_ID 10 `define PLIC_UART_ID 10
`define BPRED_ENABLED 1 `define BPRED_ENABLED 1
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE //`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0 `define TESTSBP 0
`define BPRED_SIZE 10 `define BPRED_SIZE 10

2
pipelined/src/ifu/brpred/bpred.sv
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@ -28,7 +28,7 @@
`include "wally-config.vh" `include "wally-config.vh"
`define INSTR_CLASS_PRED 0 `define INSTR_CLASS_PRED 1
module bpred ( module bpred (
input logic clk, reset, input logic clk, reset,

9
pipelined/src/ifu/brpred/speculativegshare.sv
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@ -51,16 +51,15 @@ module speculativegshare
logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE; logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE;
logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE; logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE;
logic [k-1:0] GHRF, OldGHRF; logic [k-1:0] GHRF;
logic GHRExtraF; logic GHRExtraF;
logic [k-1:0] GHRD, OldGHRE, GHRE, GHRM, GHRW; logic [k-1:0] GHRD, GHRE, GHRM, GHRW;
logic [k-1:0] GHRNextF; logic [k-1:0] GHRNextF;
logic [k-1:0] GHRNextD; logic [k-1:0] GHRNextD;
logic [k-1:0] GHRNextE, GHRNextM, GHRNextW; logic [k-1:0] GHRNextE, GHRNextM, GHRNextW;
logic [k-1:0] IndexNextF, IndexF; logic [k-1:0] IndexNextF, IndexF;
logic [k-1:0] IndexD, IndexE; logic [k-1:0] IndexD, IndexE;
logic [`XLEN-1:0] PCW;
logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF; logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF;
@ -126,7 +125,7 @@ module speculativegshare
// with instruction class prediction // with instruction class prediction
assign GHRNextD = (FlushD | DirPredictionWrongE) ? GHRNextE[k-1:0] : assign GHRNextD = (FlushD | DirPredictionWrongE) ? GHRNextE[k-1:0] :
WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], GHRF[k-1:1]} : // shift right WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], GHRF[k-1:1]} : // shift right
WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], GHRExtraF}: // shift left WrongPredInstrClassD[0] & ~BranchInstrD ? {GHRF[k-2:0], GHRExtraF}: // shift left
GHRF[k-1:0]; GHRF[k-1:0];
flopenr #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); flopenr #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
@ -144,6 +143,4 @@ module speculativegshare
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE; assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
endmodule endmodule

6
pipelined/testbench/testbench.sv
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@ -32,8 +32,8 @@
`include "wally-config.vh" `include "wally-config.vh"
`include "tests.vh" `include "tests.vh"
`define PrintHPMCounters 1 `define PrintHPMCounters 0
`define BPRED_LOGGER 1 `define BPRED_LOGGER 0
module testbench; module testbench;
parameter DEBUG=0; parameter DEBUG=0;
@ -408,7 +408,7 @@ logic [3:0] dummy;
end // always @ (negedge clk) end // always @ (negedge clk)
if(`PrintHPMCounters) begin if(`PrintHPMCounters & `ZICOUNTERS_SUPPORTED) begin
integer HPMCindex; integer HPMCindex;
string HPMCnames[] = '{"Mcycle", string HPMCnames[] = '{"Mcycle",
"------", "------",