Merge branch 'openhwgroup:main' into cachesim

sim/Makefile

@@ -18,7 +18,8 @@ all: riscoftests memfiles coveragetests
 coverage:
 	#make -C ../tests/coverage --jobs
 	#iter-elf.bash --cover --search ../tests/coverage
-	vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb riscv.ucdb -logfile cov/log
+	vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb cov/buildroot_buildroot.ucdb riscv.ucdb -logfile cov/log
+#	vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb riscv.ucdb /home/rthompson/buildroot_buildroot-no-trace.ucdb -logfile cov/log
 	vcover report -details cov/cov.ucdb > cov/rv64gc_coverage_details.rpt
 	vcover report cov/cov.ucdb -details -instance=/core/ebu. > cov/rv64gc_coverage_ebu.rpt
 	vcover report cov/cov.ucdb -details -instance=/core/priv. > cov/rv64gc_coverage_priv.rpt

sim/coverage-exclusions-rv64gc.do

@@ -24,8 +24,12 @@
 #// and limitations under the License.
 #////////////////////////////////////////////////////////////////////////////////////////////////
 
+# This file should be a last resort.  It's preferable to put 
+# // coverage off 
+# statements inline with the code whenever possible.
+
 # LZA (i<64) statement confuses coverage tool 
-# This is ugly to exlcude the whole file - is there a better option
+# This is ugly to exlcude the whole file - is there a better option?  // coverage off isn't working
 coverage exclude -srcfile lzc.sv 
 
 

sim/imperas.ic

@@ -4,20 +4,36 @@
 --showcommands
 
 # Core settings
+--override cpu/priv_version=1.12 
+--override cpu/user_version=20191213
+# arch
+--override cpu/mimpid=0x100
+--override refRoot/cpu/tvec_align=64
+
+#  clarify
+#--override refRoot/cpu/mtvec_sext=F
+
+--override cpu/tval_ii_code=T
+
+#--override cpu/time_undefined=T
+#--override cpu/cycle_undefined=T
+#--override cpu/instret_undefined=T
+#--override cpu/hpmcounter_undefined=T
+
+--override cpu/reset_address=0x80000000
+
 --override cpu/unaligned=F
 --override cpu/ignore_non_leaf_DAU=1
 --override cpu/wfi_is_nop=T
---override cpu/mimpid=0x100
 --override cpu/misa_Extensions_mask=0x0
+#--override cpu/updatePTEA=T
+#--override cpu/updatePTED=T
+--override cpu/Sstc=T
 
 # THIS NEEDS FIXING to 16
 --override cpu/PMP_registers=16
 --override cpu/PMP_undefined=T
 
-# Illegal instruction should not contain the bit pattern
-# illegal pmp read contained this
-# --override cpu/tval_ii_code=F
-
 # PMA Settings 
 # 'r': read access allowed
 # 'w': write access allowed
@@ -48,15 +64,10 @@
 #-override  refRoot/cpu/cv/extensions=RV32I
 
 # Add Imperas simulator application instruction tracing
---override cpu/show_c_prefix=T
---trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 10500000
-
-# Exceptions and pagetables debug
---override cpu/debugflags=6
-
-# Turn on verbose output for Imperas simulator and Model
 --verbose
---override  cpu/verbose=1
+--trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 0
+--override cpu/debugflags=6 --override cpu/verbose=1
+--override cpu/show_c_prefix=T
 
 # Store simulator output to logfile
 --output imperas.log

sim/regression-wally

@@ -56,7 +56,12 @@ def getBuildrootTC(boot):
         BRgrepstr="WallyHostname login:"
     else:
         name="buildroot"
-        BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0\n!"
+        if (coverage):
+            print( "buildroot coverage")
+            BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0 -coverage\n!"
+        else:
+            print( "buildroot no coverage")
+            BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0\n!"
         BRgrepstr=str(INSTR_LIMIT)+" instructions"
     return  TestCase(name,variant="rv64gc",cmd=BRcmd,grepstr=BRgrepstr)
 
@@ -130,14 +135,11 @@ tests64gc = ["arch64f", "arch64d", "arch64i", "arch64zba", "arch64zbb", "arch64z
              "arch64priv", "arch64c",  "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] 
 if (coverage):  # delete all but 64gc tests when running coverage
     configs = []
+#    tests64gc = ["coverage64gc", "arch64f", "arch64d", "arch64i", "arch64priv", "arch64c",  "arch64m", 
     tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c",  "arch64m", 
                  "arch64zi", "wally64a", "wally64periph", "wally64priv", 
                  "arch64zba",  "arch64zbb",  "arch64zbc",  "arch64zbs", 
                  "imperas64f", "imperas64d", "imperas64c", "imperas64i"] 
-#    tests64gc = ["coverage64gc", "arch64f", "arch64d", "arch64i", "arch64priv", "arch64c",  "arch64m", 
-#                 "arch64zi", "wally64a", "wally64periph", "wally64priv", 
-#                 "arch64zba",  "arch64zbb",  "arch64zbc",  "arch64zbs", 
-#                 "imperas64f", "imperas64d", "imperas64c", "imperas64i"] 
     coverStr = '-coverage'
 else:
    coverStr = ''
@@ -179,8 +181,6 @@ def main():
     try:
         os.chdir(regressionDir)
         os.mkdir("logs")
-        #print(os.getcwd())
-        #print(regressionDir)
     except:
         pass
     try:
@@ -201,9 +201,11 @@ def main():
         TIMEOUT_DUR = 30*7200 # seconds
         configs=[getBuildrootTC(boot=True)]
     elif '-coverage' in sys.argv:
-        TIMEOUT_DUR = 20*60 # seconds       
+        TIMEOUT_DUR = 20*60 # seconds    
-        #configs.append(getBuildrootTC(boot=False))
+    #   Presently don't run buildroot because it has a different config and can't be merged with the rv64gc coverage.
-        os.system('rm cov/*.ucdb')
+    #   Also it is slow to run.   
+    #    configs.append(getBuildrootTC(boot=False))
+        os.system('rm -f cov/*.ucdb')
     else:
         TIMEOUT_DUR = 10*60 # seconds
         configs.append(getBuildrootTC(boot=False))
@@ -225,12 +227,6 @@ def main():
     # Coverage report
     if coverage:
        os.system('make coverage')
-       #print('Generating coverage report')
-       #os.system('vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb -logfile cov/log')
-       #os.system('vcover report -details cov/cov.ucdb > cov/rv64gc_coverage_details.rpt')
-       #os.system('vcover report -below 100 cov/cov.ucdb > cov/rv64gc_coverage.rpt')
-       #os.system('vcover report -recursive cov/cov.ucdb > cov/rv64gc_recursive.rpt')
-       #os.system('vcover report -details -threshH 100 -html cov/cov.ucdb')
     # Count the number of failures
     if num_fail:
         print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail)

sim/wally-batch.do

@@ -46,7 +46,7 @@ mkdir -p cov
 # Check if measuring coverage
  set coverage 0
 if {$argc >= 3} {
-    if {$3 eq "-coverage"} {
+    if {$3 eq "-coverage" || ($argc >= 7 && $7 eq "-coverage")} {
         set coverage 1
     }
 }
@@ -61,8 +61,14 @@ if {$argc >= 3} {
 if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
     vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
     # start and run simulation
-    vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt 
+    if { $coverage } {
-    vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286  -fatal 7
+        echo "wally-batch buildroot coverage"
+        vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt +cover=sbecf
+        vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286  -fatal 7 -cover
+     } else {
+        vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt 
+        vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286  -fatal 7
+    }
 
     run -all
     run -all
@@ -139,6 +145,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
 } 
 
 if {$coverage} {
+    echo "Saving coverage to ${1}_${2}.ucdb"
     do coverage-exclusions-rv64gc.do  # beware: this assumes testing the rv64gc configuration
     coverage save -instance /testbench/dut/core cov/${1}_${2}.ucdb
 }

src/hazard/hazard.sv

@@ -36,7 +36,7 @@ module hazard (
   input logic  FCvtIntStallD, FPUStallD,
   input logic  DivBusyE, FDivBusyE,
   input logic  EcallFaultM, BreakpointFaultM,
-  input logic  WFIStallM,
+  input logic  wfiM, IntPendingM,
   // Stall & flush outputs
   output logic StallF, StallD, StallE, StallM, StallW,
   output logic FlushD, FlushE, FlushM, FlushW
@@ -45,6 +45,12 @@ module hazard (
   logic                                       StallFCause, StallDCause, StallECause, StallMCause, StallWCause;
   logic                                       LatestUnstalledD, LatestUnstalledE, LatestUnstalledM, LatestUnstalledW;
   logic                                       FlushDCause, FlushECause, FlushMCause, FlushWCause;
+
+  logic WFIStallM, WFIInterruptedM;
+
+  // WFI logic
+  assign WFIStallM = wfiM & ~IntPendingM;         // WFI waiting for an interrupt or timeout
+  assign WFIInterruptedM = wfiM & IntPendingM;    // WFI detects a pending interrupt.  Retire WFI; trap if interrupt is enabled.
   
   // stalls and flushes
   // loads: stall for one cycle if the subsequent instruction depends on the load
@@ -68,7 +74,7 @@ module hazard (
   assign FlushDCause = TrapM | RetM | CSRWriteFenceM | BPWrongE;
   assign FlushECause = TrapM | RetM | CSRWriteFenceM |(BPWrongE & ~(DivBusyE | FDivBusyE));
   assign FlushMCause = TrapM | RetM | CSRWriteFenceM;
-  assign FlushWCause = TrapM;
+  assign FlushWCause = TrapM & ~WFIInterruptedM;
 
   // Stall causes
   //  Most data depenency stalls are identified in the decode stage
@@ -88,7 +94,9 @@ module hazard (
   assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause);
 
   // Stall each stage for cause or if the next stage is stalled
+  // coverage off: StallFCause is always 0
   assign #1 StallF = StallFCause | StallD;
+  // coverage on
   assign #1 StallD = StallDCause | StallE;
   assign #1 StallE = StallECause | StallM;
   assign #1 StallM = StallMCause | StallW;

src/ieu/bmu/bmuctrl.sv

@@ -99,8 +99,10 @@ module bmuctrl(
                                   BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0;  // sign extend instruction
                                 else if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))
                                   BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0;  // count instruction
-        17'b0110011_0000100_100: if (`XLEN == 32)
+//        // coverage off: This case can't occur in RV64
-                                  BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0;  // zexth (rv32)
+//        17'b0110011_0000100_100: if (`XLEN == 32)
+//                                  BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0;  // zexth (rv32)
+//        // coverage on
         17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0;  // andn
         17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0;  // orn
         17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0;  // xnor

src/ieu/bmu/zbc.sv

@@ -41,7 +41,7 @@ module zbc #(parameter WIDTH=32) (
   bitreverse #(WIDTH) brB(B, RevB);
 
   mux3 #(WIDTH) xmux({RevA[WIDTH-2:0], {1'b0}}, RevA, A, ~Funct3[1:0], X);
-  mux3 #(WIDTH) ymux({{1'b0}, RevB[WIDTH-2:0]}, RevB, B, ~Funct3[1:0], Y);
+  mux2 #(WIDTH) ymux(RevB, B, ~Funct3[1], Y);
 
   clmul #(WIDTH) clm(.X, .Y, .ClmulResult);
   

src/ieu/controller.sv

@@ -263,7 +263,9 @@ module controller(
     end else assign sltD = (Funct3D == 3'b010);
 
     // Combine base and bit manipulation signals
+    // coverage off: IllegalERegAdr can't occur in rv64gc; only applicable to E mode
     assign IllegalBaseInstrD = (ControlsD[0] & IllegalBitmanipInstrD) | IllegalERegAdrD ;
+    // coverage on
     assign RegWriteD = BaseRegWriteD | BRegWriteD; 
     assign W64D = BaseW64D | BW64D;
     assign ALUSrcBD = BaseALUSrcBD | BALUSrcBD;

src/ifu/decompress.sv

@@ -135,10 +135,16 @@ module decompress (
                       IllegalCompInstrD = 1;
                       InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
                     end
+                  // coverage off
+                  // are excluding this branch from coverage because in rv64gc XLEN is always 64 and thus greater than 32 bits
+                  // This branch will only be taken if instr16[12:10] == 3'b111 and 'XLEN !> 32, because all other 
+                  // possible values for instr16[12:10] are covered by branches above. XLEN !> 32 
+                  // will never occur in rv64gc so this branch can not be covered
                   else begin // illegal instruction
                     IllegalCompInstrD = 1;
                     InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
                   end
+                  // coverage on
         5'b01101: InstrD = {immCJ, 5'b00000, 7'b1101111}; // c.j
         5'b01110: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz
         5'b01111: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez

src/lsu/lsu.sv

@@ -149,7 +149,7 @@ module lsu (
   // MMU include PMP and is needed if any privileged supported
   /////////////////////////////////////////////////////////////////////////////////////////////
 
-  if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED
+  if(`VIRTMEM_SUPPORTED) begin : hptw
     hptw hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
       .DTLBMissM, .DTLBWriteM, .InstrUpdateDAF, .DataUpdateDAM,
       .FlushW, .DCacheStallM, .SATP_REGW, .PCSpillF,

src/privileged/csr.sv

@@ -202,7 +202,7 @@ module csr #(parameter
   assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;
   assign UngatedCSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE);
   assign CSRMWriteM = UngatedCSRMWriteM & InstrValidNotFlushedM;
-  assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW)  & InstrValidNotFlushedM;
+  assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW) & InstrValidNotFlushedM;
   assign CSRUWriteM = CSRWriteM  & InstrValidNotFlushedM;
   assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE);
   assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED;

src/privileged/privileged.sv

@@ -93,7 +93,7 @@ module privileged (
   output logic             BigEndianM,                                     // Use big endian in current privilege mode
   // Fault outputs                                                         
   output logic             BreakpointFaultM, EcallFaultM,                  // breakpoint and Ecall traps should retire
-  output logic             WFIStallM                                       // Stall in Memory stage for WFI until interrupt or timeout
+  output logic             wfiM, IntPendingM                               // Stall in Memory stage for WFI until interrupt pending or timeout
 );                                                                         
                                                                            
   logic [3:0]              CauseM;                                         // trap cause
@@ -110,8 +110,6 @@ module privileged (
   logic [11:0]             MIP_REGW, MIE_REGW;                             // interrupt pending and enable bits
   logic [1:0]              NextPrivilegeModeM;                             // next privilege mode based on trap or return
   logic                    DelegateM;                                      // trap should be delegated
-  logic                    wfiM;                                           // wait for interrupt instruction
-  logic                    IntPendingM;                                    // interrupt is pending, even if not enabled.  ends wfi
   logic                    InterruptM;                                     // interrupt occuring
   logic                    ExceptionM;                                     // Memory stage instruction caused a fault
  
@@ -156,7 +154,7 @@ module privileged (
     .mretM, .sretM, .PrivilegeModeW, 
     .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MEDELEG_REGW, .STATUS_MIE, .STATUS_SIE,
     .InstrValidM, .CommittedM, .CommittedF,
-    .TrapM, .RetM, .wfiM, .InterruptM, .ExceptionM, .IntPendingM, .DelegateM, .WFIStallM, .CauseM);
+    .TrapM, .RetM, .wfiM, .InterruptM, .ExceptionM, .IntPendingM, .DelegateM, .CauseM);
 endmodule
 
 

src/privileged/trap.sv

@@ -48,7 +48,6 @@ module trap (
   output logic                 ExceptionM,                                      // exception is occurring
   output logic                 IntPendingM,                                     // Interrupt is pending, might occur if enabled
   output logic                 DelegateM,                                       // Delegate trap to supervisor handler
-  output logic                 WFIStallM,                                       // Stall due to WFI instruction
   output logic [3:0]           CauseM                                           // trap cause
 );
 
@@ -74,7 +73,6 @@ module trap (
   assign InterruptM = (|ValidIntsM) & InstrValidM; // suppress interrupt if the memory system has partially processed a request.
   assign DelegateM = `S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM] : MEDELEG_REGW[CauseM]) & 
                      (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE);
-  assign WFIStallM = wfiM & ~IntPendingM;
 
   ///////////////////////////////////////////
   // Trigger Traps and RET

src/wally/wallypipelinedcore.sv

@@ -106,7 +106,7 @@ module wallypipelinedcore (
   logic [1:0]                    PrivilegeModeW;
   logic [`XLEN-1:0]              PTE;
   logic [1:0]                    PageType;
-  logic                          sfencevmaM, WFIStallM;
+  logic                          sfencevmaM;
   logic                          SelHPTW;
 
   // PMA checker signals
@@ -162,7 +162,8 @@ module wallypipelinedcore (
   logic                          CommittedF;
   logic                          BranchD, BranchE, JumpD, JumpE;
   logic                          DCacheStallM, ICacheStallF;
-  
+  logic                          wfiM, IntPendingM;
+
   // instruction fetch unit: PC, branch prediction, instruction cache
   ifu ifu(.clk, .reset,
     .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
@@ -265,7 +266,7 @@ module wallypipelinedcore (
     .FCvtIntStallD, .FPUStallD,
     .DivBusyE, .FDivBusyE,
     .EcallFaultM, .BreakpointFaultM,
-    .WFIStallM,
+    .wfiM, .IntPendingM,
     // Stall & flush outputs
     .StallF, .StallD, .StallE, .StallM, .StallW,
     .FlushD, .FlushE, .FlushM, .FlushW);    
@@ -292,13 +293,14 @@ module wallypipelinedcore (
       .PrivilegeModeW, .SATP_REGW,
       .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS,
       .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, 
-      .FRM_REGW,.BreakpointFaultM, .EcallFaultM, .WFIStallM, .BigEndianM);
+      .FRM_REGW,.BreakpointFaultM, .EcallFaultM, .wfiM, .IntPendingM, .BigEndianM);
   end else begin
     assign CSRReadValW = 0;
     assign UnalignedPCNextF = PC2NextF;
     assign RetM = 0;
     assign TrapM = 0;
-    assign WFIStallM = 0;
+    assign wfiM = 0;
+    assign IntPendingM = 0;
     assign sfencevmaM = 0;
     assign BigEndianM = 0;
   end

testbench/common/wallyTracer.sv

@@ -162,6 +162,7 @@ module wallyTracer(rvviTrace rvvi);
 	  CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW;
 	  CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW;
 	  CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
+	  CSRArray[12'h14D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW;
 	  // user CSRs
 	  CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW;
 	  CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW;
@@ -211,6 +212,7 @@ module wallyTracer(rvviTrace rvvi);
 	  CSRArray[12'h143] = CSRArrayOld[12'h143];
 	  CSRArray[12'h142] = CSRArrayOld[12'h142];
 	  CSRArray[12'h144] = CSRArrayOld[12'h144];
+	  CSRArray[12'h14D] = CSRArrayOld[12'h14D];
 	  // user CSRs
 	  CSRArray[12'h001] = CSRArrayOld[12'h001];
 	  CSRArray[12'h002] = CSRArrayOld[12'h002];
@@ -329,6 +331,7 @@ module wallyTracer(rvviTrace rvvi);
     CSRArrayOld[12'h143] = CSRArray[12'h143];
     CSRArrayOld[12'h142] = CSRArray[12'h142];
     CSRArrayOld[12'h144] = CSRArray[12'h144];
+    CSRArrayOld[12'h14D] = CSRArray[12'h14D];
     // user CSRs
     CSRArrayOld[12'h001] = CSRArray[12'h001];
     CSRArrayOld[12'h002] = CSRArray[12'h002];
@@ -376,6 +379,7 @@ module wallyTracer(rvviTrace rvvi);
   assign #2 CSR_W[12'h143] = (CSRArrayOld[12'h143] != CSRArray[12'h143]) ? 1 : 0;
   assign #2 CSR_W[12'h142] = (CSRArrayOld[12'h142] != CSRArray[12'h142]) ? 1 : 0;
   assign #2 CSR_W[12'h144] = (CSRArrayOld[12'h144] != CSRArray[12'h144]) ? 1 : 0;
+  assign #2 CSR_W[12'h14D] = (CSRArrayOld[12'h14D] != CSRArray[12'h14D]) ? 1 : 0;
   assign #2 CSR_W[12'h001] = (CSRArrayOld[12'h001] != CSRArray[12'h001]) ? 1 : 0;
   assign #2 CSR_W[12'h002] = (CSRArrayOld[12'h002] != CSRArray[12'h002]) ? 1 : 0;
   assign #2 CSR_W[12'h003] = (CSRArrayOld[12'h003] != CSRArray[12'h003]) ? 1 : 0;
@@ -412,6 +416,7 @@ module wallyTracer(rvviTrace rvvi);
   assign rvvi.csr_wb[0][0][12'h143] = CSR_W[12'h143];
   assign rvvi.csr_wb[0][0][12'h142] = CSR_W[12'h142];
   assign rvvi.csr_wb[0][0][12'h144] = CSR_W[12'h144];
+  assign rvvi.csr_wb[0][0][12'h14D] = CSR_W[12'h14D];
   assign rvvi.csr_wb[0][0][12'h001] = CSR_W[12'h001];
   assign rvvi.csr_wb[0][0][12'h002] = CSR_W[12'h002];
   assign rvvi.csr_wb[0][0][12'h003] = CSR_W[12'h003];
@@ -448,6 +453,7 @@ module wallyTracer(rvviTrace rvvi);
   assign rvvi.csr[0][0][12'h143]    = CSRArray[12'h143];
   assign rvvi.csr[0][0][12'h142]    = CSRArray[12'h142];
   assign rvvi.csr[0][0][12'h144]    = CSRArray[12'h144];
+  assign rvvi.csr[0][0][12'h14D]    = CSRArray[12'h14D];
   assign rvvi.csr[0][0][12'h001]    = CSRArray[12'h001];
   assign rvvi.csr[0][0][12'h002]    = CSRArray[12'h002];
   assign rvvi.csr[0][0][12'h003]    = CSRArray[12'h003];

testbench/testbench-linux-imperas.sv

@@ -413,10 +413,11 @@ module testbench;
         end
       end
 
-      always @(dut.core.MTimerInt) void'(rvvi.net_push("MTimerInterrupt",    dut.core.MTimerInt));
+      always @(dut.core.MTimerInt)   void'(rvvi.net_push("MTimerInterrupt",    dut.core.MTimerInt));
-      always @(dut.core.MExtInt)   void'(rvvi.net_push("MExternalInterrupt", dut.core.MExtInt));
+      always @(dut.core.MExtInt)     void'(rvvi.net_push("MExternalInterrupt", dut.core.MExtInt));
-      always @(dut.core.SExtInt)   void'(rvvi.net_push("SExternalInterrupt", dut.core.SExtInt));
+      always @(dut.core.SExtInt)     void'(rvvi.net_push("SExternalInterrupt", dut.core.SExtInt));
-      always @(dut.core.MSwInt)    void'(rvvi.net_push("MSWInterrupt",       dut.core.MSwInt));
+      always @(dut.core.MSwInt)      void'(rvvi.net_push("MSWInterrupt",       dut.core.MSwInt));
+      always @(dut.core.priv.priv.csr.csrs.csrs.STimerInt) void'(rvvi.net_push("STimerInterrupt", dut.core.priv.priv.csr.csrs.csrs.STimerInt));
 
       final begin
         void'(rvviRefShutdown());

testbench/testbench_imperas.sv

@@ -198,10 +198,12 @@ module testbench;
       
     end
 
-    always @(dut.core.MTimerInt) void'(rvvi.net_push("MTimerInterrupt",    dut.core.MTimerInt));
+    always @(dut.core.MTimerInt)   void'(rvvi.net_push("MTimerInterrupt",    dut.core.MTimerInt));
-    always @(dut.core.MExtInt)   void'(rvvi.net_push("MExternalInterrupt", dut.core.MExtInt));
+    always @(dut.core.MExtInt)     void'(rvvi.net_push("MExternalInterrupt", dut.core.MExtInt));
-    always @(dut.core.SExtInt)   void'(rvvi.net_push("SExternalInterrupt", dut.core.SExtInt));
+    always @(dut.core.SExtInt)     void'(rvvi.net_push("SExternalInterrupt", dut.core.SExtInt));
-    always @(dut.core.MSwInt)    void'(rvvi.net_push("MSWInterrupt",       dut.core.MSwInt));
+    always @(dut.core.MSwInt)      void'(rvvi.net_push("MSWInterrupt",       dut.core.MSwInt));
+    always @(dut.core.priv.priv.csr.csrs.csrs.STimerInt) void'(rvvi.net_push("STimerInterrupt", dut.core.priv.priv.csr.csrs.csrs.STimerInt));
+
 
     final begin
       void'(rvviRefShutdown());

tests/coverage/fpu.S

@@ -57,6 +57,23 @@ main:
     fcvt.l.q a0, ft3
     fcvt.lu.q a0, ft3
 
+
+    // Tests verfying that half and quad floating point convertion instructions are not supported by rv64gc
+    # fcvt.h.d ft3, ft0 // Somehow this instruction is taking the route on line 124
+                      // idea: enable the Q extension for this to work properly? A: Q and halfs not supported in rv64gc
+    # fcvt.h.w ft3, a0
+    # fcvt.w.h a0, ft0
+    # fcvt.q.w ft3, a0
+    # fcvt.w.q a0, ft0
+    # fcvt.q.d ft3, ft0
+
+    .word 0x38007553    // Testing the all False case for 119 - funct7 under, op = 101 0011
+    .word 0x40000053    // Line 145 All False Test case - illegal instruction?
+    .word 0xd0400053    // Line 156 All False Test case - illegal instruction?
+    .word 0xc0400053    // Line 162 All False Test case - illegal instruction?
+    .word 0xd2400053    // Line 168 All False Test case - illegal instruction?
+    .word 0xc2400053    // Line 174 All False Test case - illegal instruction?
+
     # Test illegal instructions are detected
     .word 0x00000007 // illegal floating-point load (bad Funct3)
     .word 0x00000027 // illegal floating-point store (bad Funct3)

tests/coverage/ieu.S

@@ -28,6 +28,11 @@
 
 main:
 
+    # Division test (having trouble with buildroot)
+    li x11, 0x384000
+    li x12, 0x1c2000
+    divuw x9, x11, x12
+
     # Test clz with all bits being 0
     li t0, 0
     clz t1, t0
@@ -61,5 +66,6 @@ main:
     .word 0x6080101B  // Illegal BMU similar to count word
     .word 0x6030101B  // Illegal BMU similar to count word
 
+
     j done
 

tests/coverage/ifu.S

@@ -32,9 +32,23 @@ main:
     csrs mstatus, t0
 
     # calling compressed floating point load double instruction
-    //.halfword 0x2000 // CL type compressed floating-point ld-->funct3,imm,rs1',imm,rd',op
+    //.hword 0x2000 // CL type compressed floating-point ld-->funct3,imm,rs1',imm,rd',op
                         // binary version 0000 0000 0000 0000 0010 0000 0000 0000
     mv s0, sp
     c.fld fs0, 0(s0)
 
+    c.fsd fs0, 0(s0)
+
+    // c.fldsp fs0, 0
+    .hword 0x2002
+
+    // c.fsdsp fs0, 0
+    .hword 0xA002
+
+    //# Illegal compressed instruction with op = 01, instr[15:10] = 100111, and 0's everywhere else
+    //.hword 0x9C01
+
+    # Line Illegal compressed instruction 
+    .hword 0x9C41
+
     j done

tests/coverage/priv.S

@@ -36,11 +36,79 @@ main:
     addi t0, zero, 0
     csrr t0, stimecmp 
 
+
+    # satp write with mstatus.TVM = 1
+    bseti t0, zero, 20 
+    csrs mstatus, t0
+    csrw satp, zero
+
+    # STIMECMP from S mode
+    li t0, 1
+    ecall   # enter S-mode
+    csrw stimecmp, zero
+    li t0, 3
+    ecall   # return to M-mode
+    csrsi mcounteren, 2 # mcounteren_tm = 1
+    li t0, 1
+    ecall   # supervisor mode again
+    csrw stimecmp, zero
+    li t0, 3
+    ecall  # machine mode again
+
+
+
     # Test write to STVAL, SCAUSE, SEPC, and STIMECMP CSRs
     li t0, 0
     csrw stval, t0
     csrw scause, t0
     csrw sepc, t0
     csrw stimecmp, t0
-    
+    csrw scounteren, zero
+    csrw satp, zero
+
+
+    # Switch to machine mode
+    li a0, 3   
+    ecall 
+    # Testing the HPMCOUNTERM performance counter: writing
+    # Base address is 2816 (MHPMCOUNTERBASE)
+    # There are 32 HPMCOUNTER registers
+    csrw 2816, t0
+    csrw 2817, t0
+    csrw 2818, t0
+    csrw 2819, t0
+    csrw 2820, t0
+    csrw 2821, t0
+    csrw 2822, t0
+    csrw 2823, t0
+    csrw 2824, t0
+    csrw 2825, t0
+    csrw 2826, t0
+    csrw 2827, t0
+    csrw 2828, t0
+    csrw 2829, t0
+    csrw 2830, t0
+    csrw 2831, t0  
+    csrw 2832, t0
+    csrw 2833, t0
+    csrw 2834, t0
+    csrw 2835, t0
+    csrw 2836, t0
+    csrw 2837, t0
+    csrw 2838, t0
+    csrw 2839, t0
+    csrw 2840, t0
+    csrw 2841, t0
+    csrw 2842, t0
+    csrw 2843, t0
+    csrw 2844, t0
+    csrw 2845, t0
+    csrw 2846, t0
+    csrw 2847, t0      
+
+    # Testing the HPMCOUNTERM performance counter: reading
+    csrr t0, 2817
     j done
+
+
+