Forwarding logic factoring

wally-pipelined/src/ieu/forward.sv

@@ -37,6 +37,8 @@ module forward(
   output logic       FPUStallD, LoadStallD, MulDivStallD, CSRRdStallD
 );
 
+  logic MatchDE;
+  
   always_comb begin
     ForwardAE = 2'b00;
     ForwardBE = 2'b00;
@@ -50,9 +52,10 @@ module forward(
   end
 
   // Stall on dependent operations that finish in Mem Stage and can't bypass in time
-   assign FPUStallD = FWriteIntE & ((Rs1D == RdE) | (Rs2D == RdE)); 
+  assign MatchDE = (Rs1D == RdE) | (Rs2D == RdE); // Decode-stage instruction source depends on result from execute stage instruction
-   assign LoadStallD = (MemReadE|SCE) & ((Rs1D == RdE) | (Rs2D == RdE));  
+  assign FPUStallD = FWriteIntE & MatchDE; 
-   assign MulDivStallD = MulDivE & ((Rs1D == RdE) | (Rs2D == RdE)); 
+  assign LoadStallD = (MemReadE|SCE) & MatchDE;  
-   assign CSRRdStallD = CSRReadE & ((Rs1D == RdE) | (Rs2D == RdE));
+  assign MulDivStallD = MulDivE & MatchDE; 
+  assign CSRRdStallD = CSRReadE & MatchDE;
 
 endmodule