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made performance counters count branch misprediction

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Shreya Sanghai 2021-03-16 11:24:17 -04:00
parent 518618ad38
commit 23a7c8cd92
3 changed files with 5 additions and 4 deletions
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2
wally-pipelined/src/privileged/csr.sv
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@ -33,7 +33,7 @@ module csr (
input logic [`XLEN-1:0] PCM, SrcAM, input logic [`XLEN-1:0] PCM, SrcAM,
input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM, input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM,
input logic TimerIntM, ExtIntM, SwIntM, input logic TimerIntM, ExtIntM, SwIntM,
input logic InstrValidW, FloatRegWriteW, LoadStallD, input logic InstrValidW, FloatRegWriteW, LoadStallD, BPPredWrongE,
input logic [1:0] NextPrivilegeModeM, PrivilegeModeW, input logic [1:0] NextPrivilegeModeM, PrivilegeModeW,
input logic [`XLEN-1:0] CauseM, NextFaultMtvalM, input logic [`XLEN-1:0] CauseM, NextFaultMtvalM,
output logic [1:0] STATUS_MPP, output logic [1:0] STATUS_MPP,

5
wally-pipelined/src/privileged/csrc.sv
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@ -29,7 +29,7 @@
module csrc ( module csrc (
input logic clk, reset, input logic clk, reset,
input logic InstrValidW, LoadStallD, CSRMWriteM, input logic InstrValidW, LoadStallD, CSRMWriteM, BPPredWrongE,
input logic [11:0] CSRAdrM, input logic [11:0] CSRAdrM,
input logic [1:0] PrivilegeModeW, input logic [1:0] PrivilegeModeW,
input logic [`XLEN-1:0] CSRWriteValM, input logic [`XLEN-1:0] CSRWriteValM,
@ -62,7 +62,8 @@ module csrc (
assign MCOUNTEN[1] = 1'b0; assign MCOUNTEN[1] = 1'b0;
assign MCOUNTEN[2] = InstrValidW; assign MCOUNTEN[2] = InstrValidW;
assign MCOUNTEN[3] = LoadStallD; assign MCOUNTEN[3] = LoadStallD;
assign MCOUNTEN[`COUNTERS:4] = 0; assign MCOUNTEN[4] = BPPredWrongE;
assign MCOUNTEN[`COUNTERS:5] = 0;
genvar j; genvar j;
generate generate

2
wally-pipelined/src/privileged/privileged.sv
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@ -36,7 +36,7 @@ module privileged (
output logic [`XLEN-1:0] CSRReadValW, output logic [`XLEN-1:0] CSRReadValW,
output logic [`XLEN-1:0] PrivilegedNextPCM, output logic [`XLEN-1:0] PrivilegedNextPCM,
output logic RetM, TrapM, output logic RetM, TrapM,
input logic InstrValidW, FloatRegWriteW, LoadStallD, input logic InstrValidW, FloatRegWriteW, LoadStallD, BPPredWrongE,
input logic PrivilegedM, input logic PrivilegedM,
input logic InstrMisalignedFaultM, InstrAccessFaultF, IllegalIEUInstrFaultD, input logic InstrMisalignedFaultM, InstrAccessFaultF, IllegalIEUInstrFaultD,
input logic LoadMisalignedFaultM, LoadAccessFaultM, input logic LoadMisalignedFaultM, LoadAccessFaultM,