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				@ -58,7 +58,6 @@ module busfsm #(parameter integer LOGWPL, parameter logic CACHE_ENABLED )
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  logic 			   UnCachedBusRead;
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					  logic 			   UnCachedBusRead;
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  logic 			   UnCachedBusWrite;
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					  logic 			   UnCachedBusWrite;
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  logic 			   CntEn, PreCntEn;
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  logic 			   CntReset;
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					  logic 			   CntReset;
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  logic 			   WordCountFlag;
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					  logic 			   WordCountFlag;
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  logic 			   UnCachedAccess, UnCachedRW;
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					  logic 			   UnCachedAccess, UnCachedRW;
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@ -78,9 +77,7 @@ module busfsm #(parameter integer LOGWPL, parameter logic CACHE_ENABLED )
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  (* mark_debug = "true" *) busstatetype BusCurrState, BusNextState;
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					  (* mark_debug = "true" *) busstatetype BusCurrState, BusNextState;
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  assign PreCntEn = (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_WRITE);
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   assign WordCountFlag = 1; // Detect when we are waiting on the final access.
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					   assign WordCountFlag = 1; // Detect when we are waiting on the final access.
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  assign CntEn = (PreCntEn & BusAck | BusInit) & ~WordCountFlag & ~UnCachedRW; // Want to count when doing cache accesses and we aren't wrapping up.
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  assign UnCachedAccess = ~CACHE_ENABLED | ~Cacheable;
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					  assign UnCachedAccess = ~CACHE_ENABLED | ~Cacheable;
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