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remerge changes

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This commit is contained in:
eroom1966 2023-02-06 13:43:12 +00:00
parent 69e9c85d7a
commit 232bfbcfd0
3 changed files with 22 additions and 9 deletions
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18
sim/imperas.ic
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@ -1,20 +1,23 @@
#--showoverrides
--override cpu/show_c_prefix=T --override cpu/show_c_prefix=T
--override cpu/unaligned=F --override cpu/unaligned=F
--override cpu/mstatus_FS=1 --override cpu/mstatus_FS=1
# Enable the Imperas instruction coverage # Enable the Imperas instruction coverage
-extlib refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0 #-extlib refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0
-override refRoot/cpu/cv/cover=basic #-override refRoot/cpu/cv/cover=basic
-override refRoot/cpu/cv/extensions=RV32I #-override refRoot/cpu/cv/extensions=RV32I
# Add Imperas simulator application instruction tracing # Add Imperas simulator application instruction tracing
--trace --trace
--tracechange --tracechange
--traceshowicount --traceshowicount
--tracemode --tracemode
--tracemem ASX
--monitornetschange --monitornetschange
# Exceptions and pagetables debug
--override cpu/debugflags=6
# Turn on verbose output for Imperas simulator # Turn on verbose output for Imperas simulator
--verbose --verbose
@ -24,3 +27,10 @@
# Store simulator output to logfile # Store simulator output to logfile
--output imperas.log --output imperas.log
--override cpu/PMP_registers=0
#--showoverrides
#--mpdconsole
# ignore settings of bits DAU for non leaf page table walks
--override cpu/ignore_non_leaf_DAU=1

6
sim/wally-imperas.do
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@ -46,10 +46,12 @@ vsim workopt +nowarn3829 -fatal 7 \
+testDir=$env(TESTDIR) $env(OTHERFLAGS) +testDir=$env(TESTDIR) $env(OTHERFLAGS)
view wave view wave
#-- display input and output signals as hexidecimal values #-- display input and output signals as hexidecimal values
add log -recursive /* # add log -recursive /*
do wave.do # do wave.do
run -all run -all
noview ../testbench/testbench_imperas.sv noview ../testbench/testbench_imperas.sv
view wave view wave
quit -f

7
testbench/testbench_imperas.sv
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@ -142,9 +142,10 @@ module testbench;
if (!rvviVersionCheck(RVVI_API_VERSION)) begin if (!rvviVersionCheck(RVVI_API_VERSION)) begin
msgfatal($sformatf("%m @ t=%0t: Expecting RVVI API version %0d.", $time, RVVI_API_VERSION)); msgfatal($sformatf("%m @ t=%0t: Expecting RVVI API version %0d.", $time, RVVI_API_VERSION));
end end
void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR, "riscv.ovpworld.org")); void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR, "riscv.ovpworld.org"));
void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME, "riscv")); void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME, "riscv"));
void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT, "RV64GC")); void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT, "RV64GC"));
void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH, 39));
if (!rvviRefInit(elffilename)) begin if (!rvviRefInit(elffilename)) begin
msgfatal($sformatf("%m @ t=%0t: rvviRefInit failed", $time)); msgfatal($sformatf("%m @ t=%0t: rvviRefInit failed", $time));
end end