fixed broken instructions so make works.

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h

@@ -1073,15 +1073,19 @@ uart_data_wait:
     li a4, 0x61
 uart_read_LSR_IIR:
     lb t4, 0(t3) // save IIR before reading LSR mgith clear it
-//  check if t4 is the rxfifotime out interrupt if it is then read the fifo then go back and repeat this.
+    //  check if IIR is the rxfifotimeout interrupt. if it is, then read the fifo then go back and repeat this.
-    li t7, 6
+    li t5, 6
-    beq t4, t7, uart_rxfifo_timout
+    beq t4, t5, uart_rxfifo_timout
     lb t5, 0(t2) // read LSR
     andi t6, t5, 0x61  // wait until all transmissions are done and data is ready
     bne a4, t6, uart_read_LSR_IIR
+    j uart_data_ready
 uart_rxfifo_timout:
-//read the fifo until empty
+    li t4, 0x10000000 // read from the fifo
-   j uart_read_LSR_IIR
+    lb t5, 0(t4)
+    lb t5, 0(t4)
+    //read the fifo until empty
+    j uart_read_LSR_IIR
 
 
 uart_data_ready:

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-timeout-01.S

@@ -92,16 +92,16 @@ TEST_STACK_AND_DATA
         // claim and completed have the same address.
         // then you'll return by mret.
 
-trap_handler:   
+# trap_handler:   
-        // this will only get uart interrupts
+#         // this will only get uart interrupts
-        li s0, plicBaseAddr
+#         //li s0, plicBaseAddr
-        addi s0, s0, 0x200004 // claim offset 
+#         addi s0, s0, 0x200004 // claim offset 
-        lw s1, 0(s0)
+#         lw s1, 0(s0)
 
-        // check that s1 is 10 and not something else
+#         // check that s1 is 10 and not something else
-        // read uart rx fifo
+#         // read uart rx fifo
         
 
-        // completed
+#         // completed
-        sw s1, 0(s0) // tells the plic the isr is done.
+#         sw s1, 0(s0) // tells the plic the isr is done.
-        mret
+#         mret