diff --git a/pipelined/src/ifu/bpred/bpred.sv b/pipelined/src/ifu/bpred/bpred.sv
index 0f2b4bf6c..048aa1125 100644
--- a/pipelined/src/ifu/bpred/bpred.sv
+++ b/pipelined/src/ifu/bpred/bpred.sv
@@ -117,7 +117,7 @@ module bpred (
   end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor
     speculativegshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
-      .InstrClassF(PredInstrClassF), .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE);
+      .PredInstrClassF, .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE);
 
   end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor
     // *** Fix me
@@ -151,15 +151,6 @@ module bpred (
           .IEUAdrE,
           .InstrClassE);
 
-  // Part 3 RAS
-  // *** need to add the logic to restore RAS on flushes.  We will use incr for this.
-  // *** needs to include flushX
-  RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
-							.PredInstrClassF, .InstrClassD, .InstrClassE,
-							.WrongPredInstrClassD, .RASPCF, .PCLinkE);
-
-  assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF;
-
   // the branch predictor needs a compact decoding of the instruction class.
   if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode
 	logic [4:0] CompressedOpcF;
@@ -196,12 +187,19 @@ module bpred (
 						(PredInstrClassF[1] & PredValidF) ;
   end
   
+  // Part 3 RAS
+  RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
+							.PredInstrClassF, .InstrClassD, .InstrClassE,
+							.WrongPredInstrClassD, .RASPCF, .PCLinkE);
+
+  assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF;
 
   assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5
   assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5
   assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
 						  (InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01); // jump, RD != x1 or x5
   assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch
+
   flopenrc #(4) InstrClassRegE(clk, reset,  FlushE, ~StallE, InstrClassD, InstrClassE);
   flopenrc #(4) InstrClassRegM(clk, reset,  FlushM, ~StallM, InstrClassE, InstrClassM);
   flopenrc #(4) InstrClassRegW(clk, reset,  FlushW, ~StallW, InstrClassM, InstrClassW);
diff --git a/pipelined/src/ifu/bpred/speculativegshare.sv b/pipelined/src/ifu/bpred/speculativegshare.sv
index 2d0c9b90e..09c1863b6 100644
--- a/pipelined/src/ifu/bpred/speculativegshare.sv
+++ b/pipelined/src/ifu/bpred/speculativegshare.sv
@@ -37,7 +37,7 @@ module speculativegshare #(parameter int k = 10 ) (
   output logic 			  DirPredictionWrongE,
   // update
   input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
-  input logic [3:0] 	  InstrClassF, InstrClassD, InstrClassE,
+  input logic [3:0] 	  PredInstrClassF, InstrClassD, InstrClassE,
   input logic [3:0] 	  WrongPredInstrClassD, 
   input logic 			  PCSrcE
 );
@@ -72,7 +72,7 @@ module speculativegshare #(parameter int k = 10 ) (
 
   // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage
   // and then register for use in the Fetch stage.
-  assign MatchF = InstrClassF[0] & ~FlushD & (IndexNextF == IndexF);
+  assign MatchF = PredInstrClassF[0] & ~FlushD & (IndexNextF == IndexF);
   assign MatchD = InstrClassD[0] & ~FlushE & (IndexNextF == IndexD);
   assign MatchE = InstrClassE[0] & ~FlushM & (IndexNextF == IndexE);
   assign MatchNextX = MatchF | MatchD | MatchE;
@@ -105,7 +105,7 @@ module speculativegshare #(parameter int k = 10 ) (
   // For FlushE this is GHRE.  GHRNextE is both.
   assign FlushDOrDirWrong = FlushD | DirPredictionWrongE;
   mux3 #(k) GHRFMux(GHRF, {DirPredictionF[1], GHRF[k-1:1]}, GHRNextE[k-1:0], 
-					{FlushDOrDirWrong, InstrClassF[0]}, GHRNextF);
+					{FlushDOrDirWrong, PredInstrClassF[0]}, GHRNextF);
 
   // Need 1 extra bit to store the shifted out GHRF if repair needs to back shift.
   flopenr  #(k) GHRFReg(clk, reset, ~StallF | FlushD, GHRNextF, GHRF);