From 8f12c6f9a1f5b5617f2858105336908f2ac305d4 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 3 Sep 2023 04:21:13 -0700 Subject: [PATCH 1/2] initial spill logic improvement --- src/ifu/ifu.sv | 4 ++-- src/ifu/spill.sv | 10 ++++++++-- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 320b9e330..6c81c6b99 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -144,8 +144,8 @@ module ifu import cvw::*; #(parameter cvw_t P) ( ///////////////////////////////////////////////////////////////////////////////////////////// if(P.C_SUPPORTED) begin : Spill - spill #(P) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF, - .InstrUpdateDAF, .IFUCacheBusStallF, .ITLBMissF, .PCSpillNextF, .PCSpillF, .SelSpillNextF, .PostSpillInstrRawF, .CompressedF); + spill #(P) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF, .InstrUpdateDAF, .CacheableF, + .IFUCacheBusStallF, .ITLBMissF, .PCSpillNextF, .PCSpillF, .SelSpillNextF, .PostSpillInstrRawF, .CompressedF); end else begin : NoSpill assign PCSpillNextF = PCNextF; assign PCSpillF = PCF; diff --git a/src/ifu/spill.sv b/src/ifu/spill.sv index bdf14e1cc..a82f4e9bf 100644 --- a/src/ifu/spill.sv +++ b/src/ifu/spill.sv @@ -40,6 +40,7 @@ module spill import cvw::*; #(parameter cvw_t P) ( input logic IFUCacheBusStallF, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched input logic ITLBMissF, // ITLB miss, ignore memory request input logic InstrUpdateDAF, // Ignore memory request if the hptw support write and a DA page fault occurs (hptw is still active) + input logic CacheableF, // Is the instruction from the cache? output logic [P.XLEN-1:0] PCSpillNextF, // The next PCF for one of the two memory addresses of the spill output logic [P.XLEN-1:0] PCSpillF, // PCF for one of the two memory addresses of the spill output logic SelSpillNextF, // During the transition between the two spill operations, the IFU should stall the pipeline @@ -48,7 +49,6 @@ module spill import cvw::*; #(parameter cvw_t P) ( // Spill threshold occurs when all the cache offset PC bits are 1 (except [0]). Without a cache this is just PCF[1] typedef enum logic [1:0] {STATE_READY, STATE_SPILL} statetype; - localparam SPILLTHRESHOLD = P.ICACHE_SUPPORTED ? P.ICACHE_LINELENINBITS/32 : 1; statetype CurrState, NextState; logic [P.XLEN-1:0] PCPlus2NextF, PCPlus2F; @@ -76,7 +76,13 @@ module spill import cvw::*; #(parameter cvw_t P) ( // Detect spill //////////////////////////////////////////////////////////////////////////////////////////////////// - assign SpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1]; + if (P.ICACHE_SUPPORTED) begin + logic SpillCachedF, SpillUncachedF; + assign SpillCachedF = &PCF[$clog2(P.ICACHE_LINELENINBITS/32)+1:1]; + assign SpillUncachedF = PCF[1]; // *** try to optimize this based on whether the next instruction is 16 bits and by fetching 64 bits in RV64 + assign SpillF = CacheableF ? SpillCachedF : SpillUncachedF; + end else + assign SpillF = PCF[1]; // *** might relax - only spill if next instruction is uncompressed assign TakeSpillF = SpillF & ~IFUCacheBusStallF & ~(ITLBMissF | (P.SVADU_SUPPORTED & InstrUpdateDAF)); always_ff @(posedge clk) From d7d1f8f775956ec3c7167a59c09b757322c5e6c7 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 5 Sep 2023 11:12:23 -0700 Subject: [PATCH 2/2] Added build to the Embench make run command to avoid errors when just doing make run --- benchmarks/embench/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile index 3dba4daaa..97c7660c5 100644 --- a/benchmarks/embench/Makefile +++ b/benchmarks/embench/Makefile @@ -5,7 +5,7 @@ embench_dir = ../../addins/embench-iot all: build -run: size sim +run: build size sim allClean: clean all