From 8c8a7daec264adf62a196686ac3a1a7379ae55a9 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Mon, 16 May 2022 22:41:18 +0000 Subject: [PATCH 1/5] Fixed grammar on two comments in bpred.sv --- pipelined/src/ifu/bpred.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv index de2ac72ab..2e306dc60 100644 --- a/pipelined/src/ifu/bpred.sv +++ b/pipelined/src/ifu/bpred.sv @@ -116,7 +116,7 @@ module bpred // this predictor will have two pieces of data, // 1) A direction (1 = Taken, 0 = Not Taken) - // 2) Any information which is necessary for the predictor to built it's next state. + // 2) Any information which is necessary for the predictor to build its next state. // For a 2 bit table this is the prediction count. assign SelBPPredF = ((BPInstrClassF[0] & BPPredF[1] & BTBValidF) | From ea3e7006d9aec926b34366816508c712349114e8 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 17 May 2022 00:06:14 +0000 Subject: [PATCH 2/5] Cleaned up unpacker changes in srt and lint errors --- .gitignore | 1 + pipelined/srt/lint-srt | 2 +- pipelined/srt/srt.do | 2 +- pipelined/srt/srt.sv | 3 ++- pipelined/srt/testbench.sv | 23 ++++++++++++++--------- 5 files changed, 19 insertions(+), 12 deletions(-) diff --git a/.gitignore b/.gitignore index 0a25e7d3d..1e986c3bd 100644 --- a/.gitignore +++ b/.gitignore @@ -103,3 +103,4 @@ pipelined/config/rv64ic_noMulDiv pipelined/config/rv64ic_noPriv pipelined/config/rv64ic_orig synthDC/Summary.csv +pipelined/srt/exptestgen diff --git a/pipelined/srt/lint-srt b/pipelined/srt/lint-srt index 8fba602e8..3599cdff5 100755 --- a/pipelined/srt/lint-srt +++ b/pipelined/srt/lint-srt @@ -1,2 +1,2 @@ verilator --lint-only --top-module srt srt.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv -verilator --lint-only --top-module testbench testbench.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv ../src/fpu/unpacking.sv +verilator --lint-only --top-module testbench testbench.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv ../src/fpu/unpack.sv diff --git a/pipelined/srt/srt.do b/pipelined/srt/srt.do index df969ad49..b4d9bb138 100644 --- a/pipelined/srt/srt.do +++ b/pipelined/srt/srt.do @@ -17,7 +17,7 @@ if [file exists work] { } vlib work -vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv ../src/fpu/unpacking.sv +vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv ../src/fpu/unpack.sv vopt +acc work.testbench -o workopt vsim workopt diff --git a/pipelined/srt/srt.sv b/pipelined/srt/srt.sv index bc272b011..81d9e2f25 100644 --- a/pipelined/srt/srt.sv +++ b/pipelined/srt/srt.sv @@ -92,8 +92,9 @@ module srtpostproc #(parameter N=52) ( output [N-1:0] Quot ); + // replace with on-the-fly conversion //assign Quot = rp - rm; - finaladd finaladd(rp, rm, Quot); + finaladd finaladd(rp, rm, Quot); endmodule module srtpreproc #(parameter Nf=52) ( diff --git a/pipelined/srt/testbench.sv b/pipelined/srt/testbench.sv index 8b3fec51d..9985a89cf 100644 --- a/pipelined/srt/testbench.sv +++ b/pipelined/srt/testbench.sv @@ -1,7 +1,7 @@ ///////////// -// counter // +// divcounter // ///////////// -module counter(input logic clk, +module divcounter(input logic clk, input logic req, output logic done); @@ -36,6 +36,9 @@ endmodule ////////// // testbench // ////////// + +/* verilator lint_off STMTDLY */ +/* verilator lint_off INFINITELOOP */ module testbench; logic clk; logic req; @@ -83,11 +86,11 @@ module testbench; // Unpacker // Note: BiasE will probably get taken out eventually - unpack unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1), .FOpCtrlE(3'b0), + unpack unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1), .XSgnE(XSgnE), .YSgnE(YSgnE), .ZSgnE(ZSgnE), .XExpE(XExpE), .YExpE(YExpE), .ZExpE(ZExpE), .XManE(XManE), .YManE(YManE), .ZManE(ZManE), .XNormE(XNormE), .XNaNE(XNaNE), .YNaNE(YNaNE), .ZNaNE(ZNaNE), .XSNaNE(XSNaNE), .YSNaNE(YSNaNE), .ZSNaNE(ZSNaNE), .XDenormE(XDenormE), .YDenormE(YDenormE), .ZDenormE(ZDenormE), - .XZeroE(XZeroE), .YZeroE(YZeroE), .ZZeroE(ZZeroE), .BiasE(BiasE), + .XZeroE(XZeroE), .YZeroE(YZeroE), .ZZeroE(ZZeroE), .XInfE(XInfE), .YInfE(YInfE), .ZInfE(ZInfE), .XExpMaxE(XExpMaxE)); // Divider @@ -101,8 +104,8 @@ module testbench; assign result = {1'b0, e, r}; - // Counter - counter counter(clk, req, done); + // Divcounter + divcounter divcounter(clk, req, done); initial @@ -123,7 +126,7 @@ module testbench; a = Vec[`mema]; b = Vec[`memb]; nextr = Vec[`memr]; - req <= #5 1; + req = #5 1; end // Apply directed test vectors read from file. @@ -132,7 +135,7 @@ module testbench; begin if (done) begin - req <= #5 1; + req = #5 1; diffp = correctr - result; diffn = result - correctr; if (($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp @@ -152,7 +155,7 @@ module testbench; end if (req) begin - req <= #5 0; + req = #5 0; correctr = nextr; $display("pre increment"); testnum = testnum+1; @@ -167,3 +170,5 @@ module testbench; endmodule +/* verilator lint_on STMTDLY */ +/* verilator lint_on INFINITELOOP */ From 1bcbdcf57dbca9b882062717030eef79f7b4c609 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 17 May 2022 00:06:44 +0000 Subject: [PATCH 3/5] removed exptestgen --- pipelined/srt/exptestgen | Bin 22128 -> 0 bytes 1 file changed, 0 insertions(+), 0 deletions(-) delete mode 100755 pipelined/srt/exptestgen diff --git a/pipelined/srt/exptestgen b/pipelined/srt/exptestgen deleted file mode 100755 index 0b5085bcb6c9ec2f476716fba8fec66a0110e49f..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 22128 zcmeHP4{#LMd4IY?APk%i#~9gQYu%W!1m-0EM%1x&CphWkAfO;6vIAZn(n-4bbSK~K z8Nt-G5~0)=1)GV}lw_tY(@s*{WLkG7_As4{k)Ywo)a}S=CUpy)%Bh_>3?2(2V+CWb z-}mRwg((#6to(_dKtJ^lu@i zw@H?;1~FfF#ogjAF&B_I@bO9sQa#6XmRvKfAU!8gv}bAGfGhB^rVs$dj=RGK@3O%U+Ta@jSKwn!LjV*z?o)s-7FD84>5?Yg zZw0jL05;=Bp|-ZSsXd{1s4tw*Lh<&t&5>9%)E?X$2?hdde(Y2$ihR<(*Ll7IAtDl*oVsGA6(BMufQjHXLvsLyzfFD6Usji zl+OoU?#Rifs=H84UIWTxPXEdna6Si7GHt+(=i{sa$G*vlFh z6a$Xu52qRfZoEF$8*uc+slkBf+8%^n0}g@8rGNpyC5OWG%78C4;J>Q8`)Xk1VntxA zJava60;A)aBRd%w`TL4f1}!178@>YK?23c%U0Lmg9P<6BbABodX~hBLG4$srB_Br~ zLvnsx@?S#UiTsO_--|pp$@!y_e-wEP$@#;Q--$dn&G});Ka4zv=KLV=Snf6Nw5DEr zERgy|VC2o|9qp~@@g0l2B9NY#T8JclWge7s$zN3|V&*XFpX&8gR^y2&#Noi92j_#s zz@c&nl1;PP5(vSQpo<}xpPj0#9!AAeL_z;wQFv&>Pm$DK4@_Kl22#_3iA-al>~!F@ z>)LJLpp6_3mw)LWSYP>a*$V}O+HId%9{Z@zFCU(~!M4y+(I13BzG>CsupVYf+-UV|K-L+Mcg z1;(=`Jvs++c%Gz3DtSvIe@yH*SailbZND1@vFRN}YHH6&HZw z31l;uu4S`n|24>p^FM^IG5@syhU(yt^>$zEpOVnnH)UML{4-^fDgU{&e-=$H92oP@ zTJ$F+WY&KbJo+auS3c&Sf-dDBAM?Mu%6~3(Qo6fbxpExQlbv0jt?pUVylO`{P)x%=f__kDEae9`tK~>iN?r zRMglH8e<*Pg{FgKI>n~jt)>r2({qKU8_0B$O>sP==TD!&ev@&6M!sGO)GLFPnu6w7 z5Aq8xEHs3;Qw9_=?(z&Yb8lsxe`?=&=1g^?-l&_rF2)$~+CY-X+|NPC?il*dv=Z(+;Z8xnKJ7wq>a^@4r29 zwLEoZVz#>WWNI=zen05ePNdF^jF+LiJ%$T1UhjNgXifc#@AIvxE4~h2>O)`q)h&z*d)X1ei9KhmDBnls(_#1F>K_KWGprF*p3{7c_y?2zd#vOC|nJpBax zUnIZ6tCyo*((&wnc*~YKAJ`2b_T`${Z1yP7<3Oc zG^GO9(;A?k0~!GO4A6d{c*T7YC?-5#FqIwHDawZ2Wy==Mt2hiYylyUsPXipI4i&b{ zb0by{pLW3TDvs%1_`q#c48ISj83HbMv#aXi$_4u>hDGC@53F2w@9!Xtz9R7XC$Rk~ z^nc-VxxebzylAfTA02Q=DaX1D!|D1u(45@y&nTAi9{}6{b+nVe3i4@?uQJ;AN^@y{ z5%3Q{zRoC*>T;~ZLa28Y#4d#LW|#Xphu>B8tkdsO4$bkqYQA0`aMgcxZot(rGOxwu zjk+3qu6m!Vrpcu=xvH96?j~1-j9WYS@q!rY5hz8V6oFC% zN)aeUpcH|dGXm4|yt3fqMCs==tb*u?DXxiNTBsAzIoB(5yhhOp^E;UCkl(nj+9h+# zh{yR*On2%;%#s{`Ph(>Fd)KouVuMnL}{R-W+Y~K94N)4>=)+!C24W4>s zZT;Fc^&8f#S88^KdXzv=)A7~oYCpd2`dT@sgmXIBX11zbjj|e?hGDLj!YP zC0sUnrCtIm!zx%X?S5SCjsz3^LVU_3TiM;K4#r~|ObLc#Q9METTqA$Y+jq9NHa{Y= zXm-2Fc9mQa?d(*2yLS0OYx}lcAh(of9-a&3CcArNceeP74TLqdHy#`ase>_CfepnA zea*!+Wn7t%Nyhgcy>9VPFcR*IB97;(sh#@ucH(DCm|A0BYNt=Qow`fygijdU@aI#a z)J``=JB3Q^bW^kwjU&7?j_?yL-Jj%Lp2jdM|KGr@LWeR9hNaIro&?# zrp0u4?k`GnJVkXDd7+d-bP+A4vxCM{`1~xUg8MFwzwj|zOdaIwlOBKJyvhH;JdT_n zvdq1Ftp10FHk!R$83p@7`yS9 zEkyTl97}vua>Aga!Qm}X!8h;Pi{eh96~*V|)_sl6oG`i>FRDLR@Vc;Bf1W6|p6Y}} zG+u`_>(3Xwo@>T$5xnke#uwz)zs>kUF-&naDR z@7ds|Z1A%-`1>|EKFg2wvX*lN;XHSV=9nHNoPWRRs1T3X_(|H}e`JHdY=fV*!9TFU ztMS)Dk$QdB2H!)twY~=lx7POsz>D>hmq?#~b8viqLO5Sv8GnOtYy5w0gD=6GSCM+H zwZV7U;4vHgIUD?#4gO=ot@VAAaQoRk1r^`ijI0uVXKepJ|Jqm!y8-_3&qa7c0MAz21<1 z7K`O>uPlf0tC*j6K_B0^FSy>8W4#KmxAOrv|8>$&;dR&#_^lX!x{pY6 z@Qg3WDtHJ>`nkjluiH`ED6#3`$(8n!ZMC@Ne1R$87K)0lwI=G`Ft=ALI<+3Nr?} z3jH_=$5+3w@jrw9i|t!cmrTTQQ<6G(x~mR$BT+Z5UmXwi^anM4hmyL6I*%v+51O!j zNq1aZ`h_O@$|@R9yC-lh8HIjox zjcjBdxxI#^sIpjQ0hnvyZZ#f?#JY|3HRI-bn`P#Dnq`G?Fw2X?!>k}36voA@R2Uz# zTsi?Lt{G!!*0IFPER+t+aZ`IDdeDMe2sb3bAP$B@dQtKXWv7PyC=}^kExTE4SKa`? zg1(o>upq^B&23=Tx04l#y~VIF?sscQ31Uz=a`Z`*h|X5UH*2p-Pg3$k6z_YI~Z3i_ebsk6iaHbe~(Z@JwYuO|gZDht&74}x* zhQ&>niteO@;WXRn+a;MX;YsWt(1Lq`YH^+Rb51_X3-^;KJY?+gHMOqRf_=pGMU$Sr z$uMl^6^2U{6b1Om-MgsGmB2e-GF)r(5V}fo{Qha2y;6!@ao=Z@lp3kq6M7L6Zp&oR0%=j_Ku+ zmGJ~MEgs&RgtN#ncMXvJ@Gsk?_aJ=gyr**B3M z&o>?+gK>jBu60`Np9Ks%@9MHuEWB@u^plKYm= z9RSDln~*o!^E`>0UX<~3!N>#KvBU3J?0G)46BmIY5z!g=re?|UM*SN!CU}437 E0R>#^_W%F@ From 7656e3031cb7f10e8579849fbb9a1ee21914ac04 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 17 May 2022 01:03:09 +0000 Subject: [PATCH 4/5] quit --- pipelined/config/rv64gc/wally-config.vh | 4 ++-- pipelined/testbench/testbench.sv | 20 ++++++++++++++++---- pipelined/testbench/tests.vh | 2 +- 3 files changed, 19 insertions(+), 7 deletions(-) diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 35b74c6d2..d7ad9d3c8 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -131,8 +131,8 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt" +`define TWO_BIT_PRELOAD "../config/shared/twoBitPredictor.txt" +`define BTB_PRELOAD "../config/shared/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index d070aa3f2..e3eaf93bd 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -327,11 +327,23 @@ logic [3:0] dummy; .done(DCacheFlushDone)); // initialize the branch predictor - if (`BPRED_ENABLED == 1) + if (`BPRED_ENABLED == 1) initial begin - $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); - $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem); - end + integer adrindex; + + // Initializing all zeroes into the branch predictor memory. + for(adrindex = 0; adrindex < 1024; adrindex++) begin + force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0; + force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; + end + #1; + for(adrindex = 0; adrindex < 1024; adrindex++) begin + release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex]; + release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex]; + end + // $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); + // $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem); + end endmodule module riscvassertions; diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 49ff0ff5c..dba197f5f 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -962,7 +962,7 @@ string imperas32f[] = '{ "rv64i_m/I/andi-01", "6010", "rv64i_m/I/auipc-01", "2010", "rv64i_m/I/beq-01", "47010", - "rv64i_m/I/bge-01", "46010", + "rv64i_m/I/bge-01", "47010", "rv64i_m/I/bgeu-01", "56010", "rv64i_m/I/blt-01", "4d010", "rv64i_m/I/bltu-01", "57010", From e4f0f555305257fc775588c7878f7a5e29187954 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 17 May 2022 01:04:13 +0000 Subject: [PATCH 5/5] Updated testbench to initialize using force and releases storing zero in all memory locations in branch predictor. Fixed arch64i bug related to failing bge due to an incorrect signature. --- pipelined/testbench/testbench.sv | 2 -- 1 file changed, 2 deletions(-) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index e3eaf93bd..5aa1750dc 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -341,8 +341,6 @@ logic [3:0] dummy; release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex]; release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex]; end - // $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); - // $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem); end endmodule