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Merge branch 'main' of https://github.com/openhwgroup/cvw

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This commit is contained in:
Rose Thompson 2024-05-17 17:10:28 -05:00
commit 224b2e4dc4
5 changed files with 23 additions and 24 deletions
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10
src/ifu/decompress.sv
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@ -173,17 +173,17 @@ module decompress import cvw::*; #(parameter cvw_t P) (
InstrD = {7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw InstrD = {7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw
else if (instr16[6:2] == 5'b11000 & P.ZCB_SUPPORTED) else if (instr16[6:2] == 5'b11000 & P.ZCB_SUPPORTED)
InstrD = {12'b000011111111, rds1p, 3'b111, rds1p, 7'b0010011}; // c.zext.b = andi rd, rs1, 255 InstrD = {12'b000011111111, rds1p, 3'b111, rds1p, 7'b0010011}; // c.zext.b = andi rd, rs1, 255
else if (instr16[6:2] == 5'b11001 & P.ZCB_SUPPORTED) else if (instr16[6:2] == 5'b11001 & P.ZCB_SUPPORTED & P.ZBB_SUPPORTED)
InstrD = {12'b011000000100, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.b InstrD = {12'b011000000100, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.b
else if (instr16[6:2] == 5'b11010 & P.ZCB_SUPPORTED) else if (instr16[6:2] == 5'b11010 & P.ZCB_SUPPORTED & P.ZBB_SUPPORTED)
InstrD = {7'b0000100, 5'b00000, rds1p, 3'b100, rds1p, 3'b011, P.XLEN > 32, 3'b011}; // c.zext.h InstrD = {7'b0000100, 5'b00000, rds1p, 3'b100, rds1p, 3'b011, P.XLEN > 32, 3'b011}; // c.zext.h
else if (instr16[6:2] == 5'b11011 & P.ZCB_SUPPORTED) else if (instr16[6:2] == 5'b11011 & P.ZCB_SUPPORTED & P.ZBB_SUPPORTED)
InstrD = {12'b011000000101, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.h InstrD = {12'b011000000101, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.h
else if (instr16[6:2] == 5'b11101 & P.ZCB_SUPPORTED) else if (instr16[6:2] == 5'b11101 & P.ZCB_SUPPORTED)
InstrD = {12'b111111111111, rds1p, 3'b100, rds1p, 7'b0010011}; // c.not = xori InstrD = {12'b111111111111, rds1p, 3'b100, rds1p, 7'b0010011}; // c.not = xori
else if (instr16[6:2] == 5'b11100 & P.ZCB_SUPPORTED & P.XLEN > 32) else if (instr16[6:2] == 5'b11100 & P.ZCB_SUPPORTED & P.ZBA_SUPPORTED & P.XLEN > 32)
InstrD = {7'b0000100, 5'b00000, rds1p, 3'b000, rds1p, 7'b0111011}; // c.zext.w = add.uw rd, rs1, 0 InstrD = {7'b0000100, 5'b00000, rds1p, 3'b000, rds1p, 7'b0111011}; // c.zext.w = add.uw rd, rs1, 0
else if (instr16[6:5] == 2'b10 & P.ZCB_SUPPORTED) else if (instr16[6:5] == 2'b10 & P.ZCB_SUPPORTED & P.ZMMUL_SUPPORTED)
InstrD = {7'b0000001, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.mul InstrD = {7'b0000001, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.mul
else begin // reserved else begin // reserved
IllegalCompInstrD = 1'b1; IllegalCompInstrD = 1'b1;

30
testbench/common/instrNameDecTB.sv
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@ -58,17 +58,17 @@ module instrNameDecTB(
else if (funct7[6:1] == 6'b010010) name = "BCLRI"; else if (funct7[6:1] == 6'b010010) name = "BCLRI";
else if (funct7[6:1] == 6'b011010) name = "BINVI"; else if (funct7[6:1] == 6'b011010) name = "BINVI";
else if (funct7[6:1] == 6'b001010) name = "BSETI"; else if (funct7[6:1] == 6'b001010) name = "BSETI";
else if (funct7 == 7'b0000100 && rs2 == 5'b01111) name = "ZIP"; else if (funct7 == 7'b0000100 & rs2 == 5'b01111) name = "ZIP";
else if (funct7 == 7'b0011000 && rs2 == 5'b00000) name = "AES64IM"; else if (funct7 == 7'b0011000 & rs2 == 5'b00000) name = "AES64IM";
else if (funct7 == 7'b0011000 && rs2[4] == 1'b1) name = "AES64KS1I"; else if (funct7 == 7'b0011000 & rs2[4] == 1'b1) name = "AES64KS1I";
else if (funct7 == 7'b0001000 && rs2 == 5'b00010) name = "SHA256SIG0"; else if (funct7 == 7'b0001000 & rs2 == 5'b00010) name = "SHA256SIG0";
else if (funct7 == 7'b0001000 && rs2 == 5'b00011) name = "SHA256SIG1"; else if (funct7 == 7'b0001000 & rs2 == 5'b00011) name = "SHA256SIG1";
else if (funct7 == 7'b0001000 && rs2 == 5'b00000) name = "SHA256SUM0"; else if (funct7 == 7'b0001000 & rs2 == 5'b00000) name = "SHA256SUM0";
else if (funct7 == 7'b0001000 && rs2 == 5'b00001) name = "SHA256SUM1"; else if (funct7 == 7'b0001000 & rs2 == 5'b00001) name = "SHA256SUM1";
else if (funct7 == 7'b0001000 && rs2 == 5'b00110) name = "SHA512SIG0"; else if (funct7 == 7'b0001000 & rs2 == 5'b00110) name = "SHA512SIG0";
else if (funct7 == 7'b0001000 && rs2 == 5'b00111) name = "SHA512SIG1"; else if (funct7 == 7'b0001000 & rs2 == 5'b00111) name = "SHA512SIG1";
else if (funct7 == 7'b0001000 && rs2 == 5'b00100) name = "SHA512SUM0"; else if (funct7 == 7'b0001000 & rs2 == 5'b00100) name = "SHA512SUM0";
else if (funct7 == 7'b0001000 && rs2 == 5'b00101) name = "SHA512SUM1"; else if (funct7 == 7'b0001000 & rs2 == 5'b00101) name = "SHA512SUM1";
else if (funct7 == 7'b0110000) begin else if (funct7 == 7'b0110000) begin
case (rs2) case (rs2)
5'b00000: name = "CLZ"; 5'b00000: name = "CLZ";
@ -89,7 +89,7 @@ module instrNameDecTB(
else if (funct7[6:1] == 6'b010010) name = "BEXTI"; else if (funct7[6:1] == 6'b010010) name = "BEXTI";
else if (funct7 == 7'b0010100 & rs2 == 5'b00111) name = "ORC.B"; else if (funct7 == 7'b0010100 & rs2 == 5'b00111) name = "ORC.B";
else if (imm == 12'b011010000111) name = "BREV8"; else if (imm == 12'b011010000111) name = "BREV8";
else if (funct7 == 7'b0000100 && rs2 == 5'b01111) name = "UNZIP"; else if (funct7 == 7'b0000100 & rs2 == 5'b01111) name = "UNZIP";
else name = "ILLEGAL"; else name = "ILLEGAL";
10'b0010011_110: if (rd == 0 & rs2 == 0) name = "PREFETCH.I"; 10'b0010011_110: if (rd == 0 & rs2 == 0) name = "PREFETCH.I";
else if (rd == 0 & rs2 == 1) name = "PREFETCH.R"; else if (rd == 0 & rs2 == 1) name = "PREFETCH.R";
@ -181,9 +181,9 @@ module instrNameDecTB(
else if (funct7 == 7'b0010000) name = "SH2ADD"; else if (funct7 == 7'b0010000) name = "SH2ADD";
else if (funct7 == 7'b0000101) name = "MIN"; else if (funct7 == 7'b0000101) name = "MIN";
else if (funct7 == 7'b0100000) name = "ORN"; else if (funct7 == 7'b0100000) name = "ORN";
else if (funct7 == 7'b0000100 && rs2 == 5'b00000) name = "ZEXT.H"; else if (funct7 == 7'b0000100 & rs2 == 5'b00000) name = "ZEXT.H";
else if (funct7 == 7'b0000100 && op == 7'b0110011) name = "PACK"; else if (funct7 == 7'b0000100 & op == 7'b0110011) name = "PACK";
else if (funct7 == 7'b0000100 && op == 7'b0111011) name = "PACKW"; else if (funct7 == 7'b0000100 & op == 7'b0111011) name = "PACKW";
else name = "ILLEGAL"; else name = "ILLEGAL";
10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL"; 10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL";
else if (funct7 == 7'b0000001) name = "DIVU"; else if (funct7 == 7'b0000001) name = "DIVU";

4
testbench/common/loggers.sv
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@ -153,7 +153,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
end end
end end
if (P.ICACHE_SUPPORTED && I_CACHE_ADDR_LOGGER) begin : ICacheLogger if (P.ICACHE_SUPPORTED & I_CACHE_ADDR_LOGGER) begin : ICacheLogger
int file; int file;
string LogFile; string LogFile;
logic resetD, resetEdge; logic resetD, resetEdge;
@ -193,7 +193,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
end end
if (P.DCACHE_SUPPORTED && D_CACHE_ADDR_LOGGER) begin : DCacheLogger if (P.DCACHE_SUPPORTED & D_CACHE_ADDR_LOGGER) begin : DCacheLogger
int file; int file;
string LogFile; string LogFile;
logic resetD, resetEdge; logic resetD, resetEdge;

1
testbench/common/riscvassertions.sv
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@ -61,7 +61,6 @@ module riscvassertions import cvw::*; #(parameter cvw_t P);
assert ((P.ZICBOZ_SUPPORTED == 0) | (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICBOZ requires DCACHE_SUPPORTED"); assert ((P.ZICBOZ_SUPPORTED == 0) | (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICBOZ requires DCACHE_SUPPORTED");
assert ((P.SVPBMT_SUPPORTED == 0) | (P.VIRTMEM_SUPPORTED == 1 & P.XLEN==64)) else $fatal(1, "SVPBMT requires VIRTMEM_SUPPORTED and RV64"); assert ((P.SVPBMT_SUPPORTED == 0) | (P.VIRTMEM_SUPPORTED == 1 & P.XLEN==64)) else $fatal(1, "SVPBMT requires VIRTMEM_SUPPORTED and RV64");
assert ((P.SVNAPOT_SUPPORTED == 0) | (P.VIRTMEM_SUPPORTED == 1 & P.XLEN==64)) else $fatal(1, "SVNAPOT requires VIRTMEM_SUPPORTED and RV64"); assert ((P.SVNAPOT_SUPPORTED == 0) | (P.VIRTMEM_SUPPORTED == 1 & P.XLEN==64)) else $fatal(1, "SVNAPOT requires VIRTMEM_SUPPORTED and RV64");
assert ((P.ZCB_SUPPORTED == 0) | (P.M_SUPPORTED == 1 & (P.ZBA_SUPPORTED == 1 | P.XLEN == 32) & P.ZBB_SUPPORTED == 1)) else $fatal(1, "ZCB requires M and ZBB (and also ZBA for RV64)");
assert ((P.ZCA_SUPPORTED == 1) | (P.ZCD_SUPPORTED == 0 & P.ZCF_SUPPORTED == 0 & P.ZCB_SUPPORTED == 0)) else $fatal(1, "ZCB, ZCF, or ZCD requires ZCA"); assert ((P.ZCA_SUPPORTED == 1) | (P.ZCD_SUPPORTED == 0 & P.ZCF_SUPPORTED == 0 & P.ZCB_SUPPORTED == 0)) else $fatal(1, "ZCB, ZCF, or ZCD requires ZCA");
assert ((P.ZCF_SUPPORTED == 0) | ((P.F_SUPPORTED == 1) & (P.XLEN == 32))) else $fatal(1, "ZCF requires F and XLEN == 32"); assert ((P.ZCF_SUPPORTED == 0) | ((P.F_SUPPORTED == 1) & (P.XLEN == 32))) else $fatal(1, "ZCF requires F and XLEN == 32");
assert ((P.ZCD_SUPPORTED == 0) | (P.D_SUPPORTED == 1)) else $fatal(1, "ZCD requires D"); assert ((P.ZCD_SUPPORTED == 0) | (P.D_SUPPORTED == 1)) else $fatal(1, "ZCD requires D");

2
testbench/testbench.sv
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@ -666,7 +666,7 @@ module testbench;
assign Minstret = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]; assign Minstret = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
always @(negedge clk) begin always @(negedge clk) begin
if (INSTR_LIMIT > 0) begin if (INSTR_LIMIT > 0) begin
if((Minstret != 0) && (Minstret % 'd100000 == 0)) $display("Reached %d instructions", Minstret); if((Minstret != 0) & (Minstret % 'd100000 == 0)) $display("Reached %d instructions", Minstret);
if((Minstret == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $finish; end if((Minstret == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $finish; end
end end
end end