mirror of
https://github.com/openhwgroup/cvw
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Merge branch 'main' of github.com:ross144/cvw
This commit is contained in:
commit
22409a8fca
@ -117,10 +117,10 @@ set_property PULLUP true [get_ports {SDCCmd}]
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set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.500 [get_ports {SDCDat[*]}]
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set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 21.000 [get_ports {SDCDat[*]}]
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set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 10.000 [get_ports {SDCDat[*]}]
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set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.500 [get_ports {SDCCmd}]
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set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 14.000 [get_ports {SDCCmd}]
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set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 10.000 [get_ports {SDCCmd}]
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set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {SDCCmd}]
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@ -38,7 +38,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
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CONFIG.C0.DDR4_AxiNarrowBurst {false} \
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CONFIG.Reference_Clock {Differential} \
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CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
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CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {50} \
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CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {71} \
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CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
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CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \
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CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \
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@ -272,6 +272,8 @@ static void sdc_reset(struct mmc_host * mmc) {
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struct sdc_host * host = mmc_priv(mmc);
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uint32_t card_detect = 0;
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spin_lock_init(&host->lock);
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spin_lock_irq(&host->lock);
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sdc_set_clock(host, 400000);
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@ -462,7 +464,7 @@ static int axi_sdc_probe(struct platform_device * pdev) {
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return ret;
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}
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spin_lock_init(&host->lock);
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//spin_lock_init(&host->lock);
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platform_set_drvdata(pdev, host);
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return 0;
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@ -9,20 +9,20 @@
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chosen {
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linux,initrd-end = <0x85c43a00>;
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linux,initrd-start = <0x84200000>;
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bootargs = "root=/dev/vda ro";
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bootargs = "root=/dev/vda ro console=ttyS0,115200";
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stdout-path = "/soc/uart@10000000";
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x00 0x80000000 0x00 0x08000000>;
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reg = <0x00 0x80000000 0x00 0x10000000>;
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};
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cpus {
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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clock-frequency = <0x2FAF080>;
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timebase-frequency = <0x2FAF080>;
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clock-frequency = <0x43B5FC0>;
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timebase-frequency = <0x43B5FC0>;
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cpu@0 {
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phandle = <0x01>;
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@ -51,7 +51,7 @@
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uart@10000000 {
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interrupts = <0x0a>;
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interrupt-parent = <0x03>;
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clock-frequency = <0x2FAF080>;
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clock-frequency = <0x43B5FC0>;
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reg = <0x00 0x10000000 0x00 0x100>;
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compatible = "ns16550a";
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};
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@ -74,10 +74,8 @@
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fifo-depth = <256>;
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bus-width = <4>;
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interrupt-parent = <0x03>;
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clock = <0x2FAF080>;
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max-frequency = <0x989680>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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clock = <0x43B5FC0>;
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max-frequency = <0xF4240>;
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no-sdio;
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};
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